Mitigating Parameter Variation with Dynamic Fine-Grain Body Biasing * Radu Teodorescu , Jun Nakano, Abhishek Tiwari and Josep Torrellas University of Illinois at Urbana-Champaign http://iacoma.cs.uiuc.edu * to appear in MICRO-40, December 2007 Tuesday, October 9, 2007
������� ����� Motivation • Technology scaling continues • More and more transistors every generation! • However... • Chips are increasingly affected by parameter variation Intel Corp. Radu Teodorescu Intel PhD Fellowship Forum, October 2007 2 Tuesday, October 9, 2007
������� ����� Parameter Variation • Process variation • Manufacturing at low feature sizes A>$:@ • Temperature variation • Uneven activity distribution • Supply voltage variation • IR drop, di/dt noise Intel Corp. Radu Teodorescu Intel PhD Fellowship Forum, October 2007 3 Tuesday, October 9, 2007
������� ����� Effects of Parameter Variation • Higher power consumption • Lower frequency • Uncertainty in the design process Radu Teodorescu Intel PhD Fellowship Forum, October 2007 4 Tuesday, October 9, 2007
������� ����� Outline • A Model of Process Variation • Dynamic Fine-Grain Body Biasing • Evaluation • Conclusions Radu Teodorescu Intel PhD Fellowship Forum, October 2007 5 Tuesday, October 9, 2007
������� ����� Outline • A Model of Process Variation • Dynamic Fine-Grain Body Biasing • Evaluation • Conclusions Radu Teodorescu Intel PhD Fellowship Forum, October 2007 6 Tuesday, October 9, 2007
������� ����� A Model For Process Variation • Fast, simple and parameterizable model • We model two key process parameters: • Transistor critical dimension (L eff ) and threshold voltage (V th ) • We also model temperature effects Radu Teodorescu Intel PhD Fellowship Forum, October 2007 7 Tuesday, October 9, 2007
������� ����� Variation Components Die-to-die Within die • Granularity: • Within die • Die-to-die • WID variation: • Systematic variation • Random variation Radu Teodorescu Intel PhD Fellowship Forum, October 2007 8 Tuesday, October 9, 2007
������� ����� A Model For Process Variation • Variation in any parameter P: Δ P = Δ P D2D + Δ P WID = Δ P D2D + Δ P rand + Δ P sys • We focus on WID variation • D2D is a chip-wide offset to Δ P WID • Random and systematic components • Modeled as normal distributions • Treated separately - impact different levels of the microarchitecture Radu Teodorescu Intel PhD Fellowship Forum, October 2007 9 Tuesday, October 9, 2007
����� ������� Systematic Variation • We divide the chip into a grid of points • Each point has one random value of Δ P sys • Multivariate normal distribution ( μ sys =0, σ sys ) • Characterized by a correlation function: P x r P y corr ( P � y ) = ρ ( r ) ; r = | � y | x − � x , P � • Correlation is position independent and isotropic • For ρ (r) we choose the spherical model Radu Teodorescu Intel PhD Fellowship Forum, October 2007 10 Tuesday, October 9, 2007
������� ����� Spherical Model (r) ρ 1 r 3 1 − 3 r 2 φ + : (r ≤ φ ) 2 φ 3 ρ ( r ) = 0 : otherwise r 0 0 φ Stronger correlation Weaker correlation P x P x r r P y P y • Matches measured data [Friedberg et al. 05] Radu Teodorescu Intel PhD Fellowship Forum, October 2007 11 Tuesday, October 9, 2007
������� ����� Random Variation • Random variation - transistor level • We model it analytically as a normal distribution • Both Δ P rand and Δ P sys are normal and independent with σ rand and σ sys � σ 2 σ total = rand + σ 2 sys Radu Teodorescu Intel PhD Fellowship Forum, October 2007 12 Tuesday, October 9, 2007
������� ����� Outline • A Model of Process Variation • Dynamic Fine-Grain Body Biasing • Evaluation • Conclusions Radu Teodorescu Intel PhD Fellowship Forum, October 2007 13 Tuesday, October 9, 2007
������� ����� Body Biasing • Well known technique for V th control • A voltage is applied between source/drain and substrate of a transistor • Forward body bias FBB - V th ￬ - Freq ￪ - Leak ￪ • Reverse body bias RBB - V th ￪ - Freq ￬ - Leak ￬ • Useful knob to control frequency and leakage Radu Teodorescu Intel PhD Fellowship Forum, October 2007 14 Tuesday, October 9, 2007
������� ����� Body Bias Design Space Simple Time Dynamic Static adaptation BB changes with T BB fixed for chip lifetime Space FBB in active mode and workload RBB in standby • D2D variation, power, Chip-wide • D2D variation performance [Intel Xscale] [Intel’s 80-core chip] • WID variation • WID variation, power, Fine-grain • T variation performance • WID variation (space and time) [Tschanz et al] Radu Teodorescu Intel PhD Fellowship Forum, October 2007 15 Tuesday, October 9, 2007
����� ������� Body Bias Design Space Simple Time Dynamic Static adaptation BB changes with T BB fixed for chip lifetime Space FBB in active mode and workload RBB in standby • D2D variation, power, Chip-wide • D2D variation performance [Intel Xscale] [Intel’s 80-core chip] • WID variation • WID variation, power, S-FGBB Fine-grain • T variation performance • WID variation (space and time) [Tschanz et al] Radu Teodorescu Intel PhD Fellowship Forum, October 2007 15 Tuesday, October 9, 2007
����� ������� Body Bias Design Space Simple Time Dynamic Static adaptation BB changes with T BB fixed for chip lifetime Space FBB in active mode and workload RBB in standby • D2D variation, power, Chip-wide • D2D variation performance [Intel Xscale] [Intel’s 80-core chip] • WID variation • WID variation, power, S-FGBB D-FGBB Fine-grain • T variation performance • WID variation (space and time) [Tschanz et al] Radu Teodorescu Intel PhD Fellowship Forum, October 2007 15 Tuesday, October 9, 2007
����� ������� Motivation for D-FGBB • Body bias trades off frequency 1.4 Vth = 0.120V Vth = 0.135V Vth = 0.150V for leakage Relative Switching Frequency 1.2 Vth = 0.165V Vth = 0.180V • Optimal body bias: 1.0 The lowest FBB or highest RBB 0.8 s.t. circuit delay meets frequency target 0.6 50 60 70 80 90 100 • Circuit delay changes with temperature Temperature (C) • Therefore optimal BB changes with temperature Radu Teodorescu Intel PhD Fellowship Forum, October 2007 16 Tuesday, October 9, 2007
������� ����� Motivation for D-FGBB • Body bias trades off frequency 1.4 Vth = 0.120V Vth = 0.135V Vth = 0.150V for leakage Relative Switching Frequency 1.2 Vth = 0.165V Vth = 0.180V • Optimal body bias: 1.0 The lowest FBB or highest RBB The goal of D-FGBB is to keep the 0.8 s.t. circuit delay meets frequency body bias optimal as T changes target 0.6 50 60 70 80 90 100 • Circuit delay changes with temperature Temperature (C) • Therefore optimal BB changes with temperature Radu Teodorescu Intel PhD Fellowship Forum, October 2007 16 Tuesday, October 9, 2007
������� ����� Finding the Optimal BB • Measure the delay of each BB cell • Critical path replicas to sample cell delay • Phase detector “times” the critical path replica • If slow - FBB signal raised • If fast - RBB signal raised slow FBB CLK Critical Path Phase RBB Replica Detector fast extra delay Sample Point Radu Teodorescu Intel PhD Fellowship Forum, October 2007 17 Tuesday, October 9, 2007
������� ����� Applying Fine Grain BB Sample Points Sample Points RBB FBB FBB RBB RBB FBB FBB RBB Local Bias Generator Local Bias Generator Local Bias Generator DEC NMOS Vbb NMOS Vbb AND N-CNT D2A N-CNT N-CNT D2A PMOS Vbb PMOS Vbb P-CNT D2A P-CNT P-CNT D2A OR INC RBB FBB FBB RBB RBB FBB FBB RBB Body Bias Cell Body Bias Cell Radu Teodorescu Intel PhD Fellowship Forum, October 2007 18 Tuesday, October 9, 2007
������� ����� Applying Fine Grain BB Sample Points Sample Points RBB FBB FBB RBB RBB FBB FBB RBB Local Bias Generator Local Bias Generator Local Bias Generator DEC NMOS Vbb NMOS Vbb AND N-CNT D2A N-CNT N-CNT D2A PMOS Vbb PMOS Vbb P-CNT D2A P-CNT P-CNT D2A OR INC RBB FBB FBB RBB RBB FBB FBB RBB Body Bias Cell Body Bias Cell Radu Teodorescu Intel PhD Fellowship Forum, October 2007 18 Tuesday, October 9, 2007
������� ����� Applying Fine Grain BB Sample Points Sample Points RBB FBB FBB RBB RBB FBB FBB RBB Local Bias Generator Local Bias Generator Local Bias Generator DEC NMOS Vbb NMOS Vbb AND N-CNT D2A N-CNT N-CNT D2A PMOS Vbb PMOS Vbb P-CNT D2A P-CNT P-CNT D2A OR INC RBB FBB FBB RBB RBB FBB FBB RBB Body Bias Cell Body Bias Cell Radu Teodorescu Intel PhD Fellowship Forum, October 2007 18 Tuesday, October 9, 2007
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