Memory protection on AVR32 Memory Layout LSE Summer Week 2014 - PowerPoint PPT Presentation

Memory protection on AVR32 Pierre Surply Introduction Memory protection on AVR32 Memory Layout LSE Summer Week 2014 External Bus Interface MPU Pierre Surply Conclusion EPITA 2016 Jul 19, 2014 Pierre Surply (EPITA 2016) Memory protection on AVR32 Jul 19, 2014 1 / 25

AVR32 Architecture Memory protection on AVR32 Pierre Surply Introduction 32-bit RISC microprocessor Memory Layout Modified Harvard External Bus Up to 15 general-purpose 32-bit registers Interface Instruction length : 16 bits MPU Conclusion Big-endian Fast interrupts and multiple interrupt priority levels Privileged and unprivileged modes Pierre Surply (EPITA 2016) Memory protection on AVR32 Jul 19, 2014 2 / 25

AVR32 AP7 Memory protection on AVR32 Pierre Surply Introduction Memory Application Processors Layout 221 DMIPS @ 150 MHz External Bus Interface SIMD/DSP Instructions MPU Instruction and Data caches Conclusion Memory Management Unit Java hardware acceleration Pierre Surply (EPITA 2016) Memory protection on AVR32 Jul 19, 2014 3 / 25

NGW100 Development Board Memory protection on AVR32 Pierre Surply Introduction Memory Layout External Bus Interface MPU Conclusion Figure: NGW100 Pierre Surply (EPITA 2016) Memory protection on AVR32 Jul 19, 2014 4 / 25

AVR32 UC3 Memory protection on AVR32 Pierre Surply Introduction Flash Microcontrollers Memory Layout 91 DMIPS @ 66 MHz External Bus Interface DSP Instructions MPU Instruction and Data prefetch Conclusion Memory Protection Unit Embedded Flash/RAM Pierre Surply (EPITA 2016) Memory protection on AVR32 Jul 19, 2014 5 / 25

UC3 Development Board Memory protection on AVR32 Pierre Surply Introduction Memory Layout External Bus Interface MPU Conclusion Figure: EVK1100 Pierre Surply (EPITA 2016) Memory protection on AVR32 Jul 19, 2014 6 / 25

Memory Layout Memory protection on AVR32 Pierre Surply Introduction Memory Layout External Bus Interface MPU Conclusion Figure: Memory Map ( 0x00000000 - 0xFFFFFFFF ) Pierre Surply (EPITA 2016) Memory protection on AVR32 Jul 19, 2014 7 / 25

Memory Layout Memory protection on AVR32 Pierre Surply Introduction Memory Layout External Bus Interface MPU Conclusion Figure: Memory Map ( 0xC0000000 - 0xDFFFFFFF ) Pierre Surply (EPITA 2016) Memory protection on AVR32 Jul 19, 2014 8 / 25

External Bus Interface Memory protection on U11 AVR32 23 2 A2 A0 DQ0 D0 24 4 Pierre Surply A3 A1 DQ1 D1 25 5 A4 A2 DQ2 D2 26 7 A5 A3 DQ3 D3 29 8 A6 A4 DQ4 D4 30 10 Introduction A7 A5 DQ5 D5 31 11 A8 A6 DQ6 D6 32 13 A9 A7 DQ7 D7 33 Memory A10 A8 34 42 A11 A9 DQ8 D8 Layout 22 44 SDA10 A10 DQ9 D9 35 45 A13 A11 DQ10 D10 36 47 A14 A12 DQ11 D11 External Bus 48 DQ12 D12 20 50 Interface A16 BA0 DQ13 D13 21 51 A17 BA1 DQ14 D14 53 DQ15 D15 15 MPU DQM0 DQML 39 3 DQM1 DQMH VDDQ1 9 VDDQ2 16 43 Conclusion SDWEn WE VDDQ3 17 49 CASn CAS VDDQ4 18 1 RASn RAS VDD1 19 14 CS1n CS VDD2 27 VCC3 VDD3 R77 4.7k 37 54 SDCKE CKE VSS1 R93 4.7k 38 41 VCC3 CLK VSS2 28 SDCK VSS3 52 VSSQ1 46 VSSQ2 12 VSSQ3 40 6 NC VSSQ4 MT48LC16M16A2 Figure: Synchronous DRAM 32MB - 4M x 16 x 4 banks Pierre Surply (EPITA 2016) Memory protection on AVR32 Jul 19, 2014 9 / 25

External Bus Interface Memory protection on AVR32 AVR32 Pierre Surply Introduction CPU Memory Layout External Bus Interface MPU EBI Conclusion SDRAM SDRAM PIO System Bus Controller Figure: EBI Conceptual schematics Pierre Surply (EPITA 2016) Memory protection on AVR32 Jul 19, 2014 10 / 25

External Bus Interface Memory protection on AVR32 BANK 3 Pierre Surply BANK 2 Introduction BANK 1 Memory CONTROL LOGIC BANK 0 Layout External Bus Interface MPU Memory cell rows Conclusion columns Figure: Generic SDRAM device Pierre Surply (EPITA 2016) Memory protection on AVR32 Jul 19, 2014 11 / 25

External Bus Interface Memory protection on AVR32 SDRAM AVR32 SDCK CLK Pierre Surply SDCKE CKE Introduction SDCS CS Memory BA[1:0] BA[1:0] Layout External Bus RAS RAS Interface SDRAMC PIO CAS CAS MPU SDWE WE Conclusion NBS[1:0] NBS[1:0] SDRAMC SDRAMC_A[12:0] A[12:0] User interface D[31:0] D[31:0] PB Figure: SDRAM Connection Pierre Surply (EPITA 2016) Memory protection on AVR32 Jul 19, 2014 12 / 25

External Bus Interface Memory protection on EBI EBI AVR32 D0-D15 D0-D15 RAS RAS Pierre Surply 2M x 8 2M x 8 2M x 8 2M x 8 CAS CAS SDCK SDCK SDRAM SDRAM SDRAM SDRAM D0-D7 D0-D7 D8-D15 D8-D15 SDCKE SDCKE D0-D7 D0-D7 D0-D7 D0-D7 SDWE SDWE A0/NBS0 A0/NBS0 CS CS CS CS NWR1/NBS1 NWR1/NBS1 CLK CLK CLK CLK A1/NWR2/NBS2 A1/NWR2/NBS2 A0-A9, A11 A0-A9, A11 A2-A11, A13 A2-A11, A13 A0-A9, A11 A0-A9, A11 A2-A11, A13 A2-A11, A13 CKE CKE CKE CKE Introduction A10 A10 NWR3/NBS3 NWR3/NBS3 SDWE SDWE SDA10 SDA10 SDWE SDWE A10 A10 SDA10 SDA10 WE WE WE WE NRD/NOE NRD/NOE BA0 BA0 A16/BA0 A16/BA0 BA0 BA0 A16/BA0 A16/BA0 RAS RAS RAS RAS NWR0/NWE NWR0/NWE BA1 BA1 A17/BA1 A17/BA1 BA1 BA1 A17/BA1 A17/BA1 CAS CAS CAS CAS DQM DQM DQM DQM NBS0 NBS0 NBS1 NBS1 Memory SDA10 SDA10 Layout A2-A15 A2-A15 A16/BA0 A16/BA0 A17/BA1 A17/BA1 A18-A23 A18-A23 External Bus Interface NCS0 NCS0 NCS1/SDCS NCS1/SDCS NCS2 NCS2 NCS3 NCS3 MPU Conclusion 128K x 8 128K x 8 128K x 8 128K x 8 SRAM SRAM SRAM SRAM A1-A17 A1-A17 A1-A17 A1-A17 D0-D7 D0-D7 A0-A16 A0-A16 D0-D7 D0-D7 A0-A16 A0-A16 D0-D7 D0-D7 D8-D15 D8-D15 CS CS CS CS OE OE OE OE NRD/NOE NRD/NOE NRD/NOE NRD/NOE WE WE WE WE A0/NWR0/NBS0 A0/NWR0/NBS0 NWR1/NBS1 NWR1/NBS1 Figure: EBI Connections to Memory Devices Pierre Surply (EPITA 2016) Memory protection on AVR32 Jul 19, 2014 13 / 25

Memory Protection Unit Memory protection on AVR32 Reset interface OCD interface Interrupt controller interface Pierre Surply Power/ OCD Introduction Reset system control Memory Layout AVR32UC CPU pipeline External Bus Interface MPU MPU Conclusion Instruction memory controller Data memory controller High High CPU Local Speed High Speed Bus master Speed Bus Bus Bus slave master Data RAM interface master High Speed Bus High Speed Bus High Speed Bus CPU Local Bus Figure: Overview of the AVR32UC CPU Pierre Surply (EPITA 2016) Memory protection on AVR32 Jul 19, 2014 14 / 25

Memory Protection Unit Memory protection on AVR32 Pierre Surply Allows the user to divide the memory space into different Introduction protection regions. Memory Layout Each region is divided into 16 subregions, each of these External Bus subregions can have one of two possible sets of access Interface MPU permissions. Conclusion AVR32 Architecture Document This is a simpler alternative to a full MMU, while at the same time allowing memory protection. Pierre Surply (EPITA 2016) Memory protection on AVR32 Jul 19, 2014 15 / 25

MPU Exception Handling Memory protection on AVR32 Pierre Surply Introduction Memory ITLB Protection Violation Layout External Bus DTLB Protection Violation Interface ITLB Miss Violation MPU DTLB Miss Violation Conclusion TLB Multiple Hit Violation Pierre Surply (EPITA 2016) Memory protection on AVR32 Jul 19, 2014 16 / 25

Memory Protection Unit Memory protection on MPUARn AVR32 31 12 11 6 5 1 0 Pierre Surply Base Address - Size V MPUPSRn Introduction 31 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 P15 P14 P13 P12 P11 P10 - P9 P8 P7 P6 P5 P4 P3 P2 P1 P0 Memory Layout MPUCRA / MPUCRB 31 8 7 6 5 4 3 2 1 0 External Bus - C7 C6 C5 C4 C3 C2 C1 C0 Interface MPUBRA / MPUBRB MPU 31 8 7 6 5 4 3 2 1 0 Conclusion - B7 B6 B5 B4 B3 B2 B1 B0 MPUAPRA / MPUAPRB 31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0 AP7 AP6 AP5 AP4 AP3 AP2 AP1 AP0 MPUCR 31 1 0 - E Figure: MPU Registers Pierre Surply (EPITA 2016) Memory protection on AVR32 Jul 19, 2014 17 / 25

System Registers Memory protection on AVR32 Pierre Surply Introduction __asm__ volatile ("mfsr %0, %1" Memory : "=r" (res) Layout External Bus : "i" (addr)); Interface MPU __asm__ volatile ("mtsr %0, %1" Conclusion : : "i" (addr), "r" (value)); Pierre Surply (EPITA 2016) Memory protection on AVR32 Jul 19, 2014 18 / 25

Memory Protection Memory protection on AVR32 Pierre Surply Introduction Memory Layout External Bus Interface MPU Conclusion Figure: Basic MPU configuration Pierre Surply (EPITA 2016) Memory protection on AVR32 Jul 19, 2014 19 / 25

Memory Protection Memory protection on AVR32 Pierre Surply Introduction Memory Layout External Bus Interface MPU Conclusion Figure: Application MPU configuration I Pierre Surply (EPITA 2016) Memory protection on AVR32 Jul 19, 2014 20 / 25

Memory Protection Memory protection on AVR32 Pierre Surply Introduction Memory Layout External Bus Interface MPU Conclusion Figure: Application MPU configuration II Pierre Surply (EPITA 2016) Memory protection on AVR32 Jul 19, 2014 21 / 25

Memory Protection Memory protection on AVR32 Pierre Surply Introduction Memory Layout External Bus Interface MPU Conclusion Figure: Application address space Pierre Surply (EPITA 2016) Memory protection on AVR32 Jul 19, 2014 22 / 25