Mapping CSP Models to Hardware using CLaSH Frist Kuipers, Rinse - PowerPoint PPT Presentation

Mapping CSP Models to Hardware using CLaSH Frist Kuipers, Rinse Wester, Jan Kuper & Jan Broenink University of Twente, Enschede 2016, August 23 1

Contents ✤ Introduction ✤ CLaSH ✤ CSP constructs ✤ Results ✤ Conclusions 2

Introduction ✤ Embedded system design more complicated ✤ Increase in number of requirements ✤ Model-Driven Design (MDD) 3

Introduction CPU FPGA Sensors Actuators 4

CLaSH ✤ Functional Hardware Description Language (Haskell) ✤ Structural description of hardware ✤ Components based on Mealy-machine 5

CLaSH mealy s i = (s’, o) where (o, s’) = f s i ( ) ′ s ′ s f o i 6

CLaSH mac s (a, b) = (s’, out) where output = s’ s’ = s + a * b s ′ s a c + × b 7

CSP constructs in CLaSH ✤ Components with trigger tokens ✤ Three basic CSP constructs ✤ Parallel Comp ✤ Sequential ✤ Channels 8

Parallel construct parallel’ (te, ti1, ti2) (tei, tii1, tii2) = ((tei, ti1r, ti2r), (teo, tio1, tio2)) where -- Return token when both are received tio2 teo = ti1 && ti2 tio1 -- Only consume token one when both received tei ti1r = ti1 && ti2 ti2r = ti1 && ti2 Q PAR P teo -- Return token to both structures in parallel tio1 = te tio2 = te tii1 tii2 9

Sequential construct P tio sequential tei tii = (teo, tio) tei where SEQ teo = register False tii teo tio = register False tei Q tii 10

Channels circuit (val_in, tkn_in_writer, tkn_in_reader) = (val_out, tkn_out_writer, tkn_out_reader) where (value, writer_ready, tkn_out_) = writer (val_in, success, tkn_in_writer) (success, value, writer_ready) = channel (success, value, writer_ready) (val_out, tkn_out_reader, succes) = reader (value, writer_ready, tkn_in_reader) token token success success s value value ! channel ? value vi value vi writer ready writer ready t t token token 11

Work flow CSP model Translation by hand Data-flow diagram TERRA M2T Translation by hand GHC simulation C λ aSH Description Timing diagram C λ aSH compiler Modelsim Timing diagram VHDL Quartus synthesis Realisation (RaMstix) 12

Results ✤ Two examples implemented ✤ Single reader and writer ✤ Double reader and writer 13

Double reader/writer 14

Double reader/writer clock Injected token - ti Input writer 0 - vi 1 Input writer 1 - vi 2 Channel 0 value - cOut0 Nothing Nothing 1 Channel 1 value - cOut1 Nothing Nothing 2 Success 0 - s0 Success 1 - s1 Output value 0 - rOut0 Nothing 1 Output value 1 - rOut1 Nothing 2 15

Hardware results Example Logic Elements Producer consumer 23 Double producer consumer 37 16

Conclusion ✤ Mapping for CSP to FPGA developed ✤ Feasibility illustrated using examples 17

Future work ✤ Integration in TERRA tool ✤ Support for alt construct 18

Questions? 19