Main Memory: Address Translation (Chapter 8) CS 4410 Operating Systems
Can’t We All Just Get Along? Physical Reality: different processes/threads share the same hardware à need to multiplex • CPU (temporal) • Memory (spatial) • Disk and devices (later) Why worry about memory sharing? • Complete working state of process and/or kernel is defined by its data in memory (+ registers) • Don’t want different threads to have access to each other’s memory (protection) 2
Aspects of Memory Multiplexing Isolation Don’t want distinct process states collided in physical memory (unintended overlap à chaos) Sharing Want option to overlap when desired (for communication) Virtualization Want to create the illusion of more resources than exist in underlying physical system Utilization Want to best use of this limited resource 3
Address Translation • Paged Translation • Efficient Address Translation All in the context of the OS 4
A Day in the Life of a Program Compiler Loader (+ Assembler + Linker) “It’s alive!” sum pid xxx sum.c process executable source files PC GP SP 0xffffffff stack ... #include <stdio.h> 0040 0000 0C40023C 21035000 main int max = 10; .text 1b80050c 8C048004 int main () { heap int i; 21047002 int sum = 0; 0C400020 data add(m, &sum); ... max printf(“%d”,i); 0x10000000 1000 0000 10201000 ... 21040330 text .data max 22500102 } jal addi ... 0x00400000 5 0x00000000
Logical view of process memory What’s wrong with this 0xffffffff …in the context of: stack multiple processes? multiple threads? heap data text 0x00000000 6
TERMINOLOGY ALERT: Paged Translation Page: the data itself Frame: physical location Process Physical View Memory Virtual Frame M Page N stack STACK 0 No more HEAP 0 external fragmentation! TEXT 1 heap HEAP 1 DATA 0 data TEXT 0 text STACK 1 Virtual Frame 0 Page 0 7
Paging Overview Divide: • Physical memory into fixed-sized blocks called frames • Logical memory into blocks of same size called pages Management: • Keep track of all free frames. • To run a program with n pages, need to find n free frames and load program Notice: • Logical address space can be noncontiguous! • Process given frames when/where available 8
Address Translation, Conceptually Virtual Address Raise Invalid Translation Processor Exception Who does this? Valid Physical Memory Data Physical Address Data 9
Memory Management Unit (MMU) • Hardware device • Maps virtual to physical address (used to access data) User Process: • deals with virtual addresses • Never sees the physical address 10
High-Level Address Translation Process Physical View Memory red cube is 255 th Page N Frame M stack STACK 0 byte in page 2. HEAP 0 Where is the red TEXT 1 heap HEAP 1 cube in physical DATA 0 data memory? TEXT 0 text STACK 1 Page 0 Frame 0 11
Logical Address Components Page number – Upper bits • Must be translated into a physical frame number Page offset – Lower bits • Does not change in translation page offset page number m - n n For given logical address space 2 m and page size2 n 12
High-Level Address Translation Who keeps Virtual Physical Memory Memory track of the mapping? stack STACK 0 HEAP 0 TEXT 1 0x???? heap à Page Table 0x6000 HEAP 1 0x5000 0x5000 DATA 0 0 - 0x4000 data 0x4000 1 3 TEXT 0 0x3000 0x3000 2 6 text 0x20FF 0x2000 0x2000 3 4 STACK 1 0x1000 4 8 0x1000 0x0000 5… 5 0x0000 13
Simplified Page Table Page-table Lives in Memory Page-table base register (PTBR) Points to the page table • Saved/restored on context switch • PTBR 14
Leveraging Paging • Protection • Dynamic Loading • Dynamic Linking • Copy-On-Write 15
Full Page Table Page-table Meta Data about each frame Protection R/W/X, Modified, Valid, etc. PTBR 16
Leveraging Paging • Protection • Dynamic Loading • Dynamic Linking • Copy-On-Write 17
Dynamic Loading & Linking Dynamic Loading • Routine is not loaded until it is called • Better memory-space utilization; unused routine is never loaded • No special support from the OS needed Dynamic Linking • Routine is not linked until execution time • Locate (or load) library routine when called • AKA shared libraries ( e.g. , DLLs) 18
Leveraging Paging • Protection • Dynamic Loading • Dynamic Linking • Copy-On-Write 19
Copy on Write (COW) Physical P1 Virt Addr Space Addr Space COW X stack • P1 forks() X heap heap • P2 created with X data text - own page table text X - same translations P2 Virt Addr Space • All pages data X stack marked COW stack heap X (in Page Table) data X X text 20
Option 1: fork, then keep executing Physical P1 Virt Addr Space Addr Space COW Now one process X stack stack tries to write to the X heap heap stack (for example) : X data text • Page fault text X • Allocate new P2 Virt Addr Space frame data X stack • Copy page stack heap X • Both pages no data X longer COW X text 21
Option 2: fork, then call exec Physical P1 Virt Addr Space Addr Space Before P2 calls COW X stack exec() X heap heap X data text text X P2 Virt Addr Space P2 Virt Addr Space data X stack stack stack heap heap X data data X X text text 22
Option 2: fork, then call exec Physical P1 Virt Addr Space Addr Space COW stack stack After P2 calls exec() heap heap data text text • Allocate new text frames P2 Virt Addr Space data • Load in new pages data stack stack • Pages no longer COW data text 23
Downsides to Paging Memory Consumption: • Internal Fragmentation • Make pages smaller? But then… • Page Table Space: consider 32-bit address space, 4KB page size, each PTE 8 bytes • How big is this page table? • How many pages in memory does it need? Performance: every data/instruction access requires two memory accesses: • One for the page table • One for the data/instruction 24
Address Translation • Paged Translation • Efficient Address Translation • Multi-Level Page Tables • Inverted Page Tables • TLBs 25
Multi-Level Page Tables to the Rescue! Implementation Physical Memory Processor Virtual Address index 1 | index 2 | offset Index 1 Index 2 Index 3 Offset Physical Address Level 1 Frame Offset Level 2 Frame Level 3 Frame | Access + Allocate only PTEs in use + Simple memory allocation − more lookups per memory reference 26
Two-Level Paging Example 32-bit machine, 1KB page size • Logical address is divided into: – a page offset of 10 bits (1024 = 2^10) – a page number of 22 bits (32-10) • Since the page table is paged, the page number is further divided into: – a 12-bit first index – a 10-bit second index • Thus, a logical address is as follows: page number page offset index 1 index 2 offset 12 10 10 27
This one goes to three! Implementation Physical Memory Processor Virtual Address Index 1 Index 2 Index 3 Offset Physical Address Level 1 Frame Offset Level 2 Level 3 + First Level requires less contiguous memory − even more lookups per memory reference 28
Complete Page Table Entry (PTE) Valid Protection R/W/X Ref Dirty Index Index is an index into: • table of memory frames (if bottom level) • table of page table frames (if multilevel page table) • backing store (if page was swapped out) Synonyms: • Valid bit == Present bit • Dirty bit == Modified bit • Referenced bit == Accessed bit 29
Address Translation • Paged Translation • Efficient Address Translation • Multi-Level Page Tables • Inverted Page Tables • TLBs 30
Inverted Page Table: Motivation P4 So many virtual pages… virtual address P1 virtual space address space P2 virtual physical address P3 virtual address space space P5 virtual address space … comparatively few physical frames address space Traditional Page Tables: • map pages to frames • are numerous and sparse Why not map frames to pages? (How?) 31
Inverted Page Table: Implementation Virtual address pid page # offset pid page Page-table Physical Memory frame page pid h c r a e g S n i offset h c t a m d r i o p F & e g Implementation: a p frame • 1 Page Table for entire system • 1 entry per frame in memory • Why don’t we store the frame #? 32 Not to scale! Page table << Memory
Inverted Page Table: Discussion Tradeoffs: ↓ memory to store page tables ↑ time to search page tables Solution: hashing • hash(page,pid) à PT entry (or chain of entries) • What about: • collisions… • sharing… 33
Address Translation • Paged Translation • Efficient Address Translation • Multi-Level Page Tables • Inverted Page Tables • TLBs 34
Translation Lookaside Buffer (TLB) Cache of virtual to physical page translations Physical Major efficiency improvement Memory Virtual Address Page# Offset Translation Lookaside Buffer (TLB) Virtual Page Page Frame Access Physical Address Matching Entry Frame Offset Page Table 35 Lookup
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