Logical Modeling with Time Delays Heike Siebert Alexander Bockmayr DFG-Research Center M ATHEON , Freie Universität Berlin Toward Systems Biology Grenoble October 2007 Heike Siebert (M ATHEON / FU Berlin) Logical Modeling with Time Delays TSB 2007 1 / 14
Why logical modeling? lack of quantitative information on kinetic parameters and molecular concentrations biochemical reaction mechanisms underlying interactions not or incompletely known resulting systems of differential equations mostly not analytically solvable ⇒ discrete modeling based on qualitative data Heike Siebert (M ATHEON / FU Berlin) Logical Modeling with Time Delays TSB 2007 2 / 14
Why logical modeling? lack of quantitative information on kinetic parameters and molecular concentrations biochemical reaction mechanisms underlying interactions not or incompletely known resulting systems of differential equations mostly not analytically solvable ⇒ discrete modeling based on qualitative data allow for the incorporation of temporal data concerning network processes Heike Siebert (M ATHEON / FU Berlin) Logical Modeling with Time Delays TSB 2007 2 / 14
Thomas Formalism [ R. Thomas, 1973 ] Structure: interaction graph − , 1 + , 1 − , 2 discrete variables α 1 ,... α n α 1 α 2 − , 1 expression levels 0 ,..., p j associated with each α j α 1 ∈ { 0 , 1 } , α 2 ∈ { 0 , 1 , 2 } labeled interactions Heike Siebert (M ATHEON / FU Berlin) Logical Modeling with Time Delays TSB 2007 3 / 14
Thomas Formalism [ R. Thomas, 1973 ] Structure: interaction graph − , 1 + , 1 − , 2 discrete variables α 1 ,... α n α 1 α 2 − , 1 expression levels 0 ,..., p j associated with each α j α 1 ∈ { 0 , 1 } , α 2 ∈ { 0 , 1 , 2 } labeled interactions s = ( s 1 , s 2 ) , f ( s ) = ( f 1 ( s ) , f 2 ( s )) Dynamics: state space and evolution � state space s 2 = 0 1 , f 1 ( s ) = S : = { 0 ,..., p 1 }×···×{ 0 ,..., p n } 0 , else discrete function f : S → S , s 1 = 0 ∧ s 2 ≤ 1 2 f 2 ( s ) = 1 , s 1 = 0 ∧ s 2 = 2 determines behavior of the system 0 , else Heike Siebert (M ATHEON / FU Berlin) Logical Modeling with Time Delays TSB 2007 3 / 14
Thomas Formalism Dynamics: state transition graph (0 , 2) (1 , 2) vertex set S edges derived from parameter values (0 , 1) (1 , 1) (0 , 0) (1 , 0) Heike Siebert (M ATHEON / FU Berlin) Logical Modeling with Time Delays TSB 2007 4 / 14
Thomas Formalism Dynamics: state transition graph (0 , 2) (1 , 2) vertex set S edges derived from parameter values (0 , 1) (1 , 1) ◮ corresponding component values differ at most by 1 (0 , 0) (1 , 0) Heike Siebert (M ATHEON / FU Berlin) Logical Modeling with Time Delays TSB 2007 4 / 14
Thomas Formalism Dynamics: state transition graph (0 , 2) (1 , 2) vertex set S edges derived from parameter values (0 , 1) (1 , 1) ◮ corresponding component values differ at most by 1 ◮ states differ from their successors in one component only asynchronous update: sole (0 , 0) (1 , 0) assumption about time delays Heike Siebert (M ATHEON / FU Berlin) Logical Modeling with Time Delays TSB 2007 4 / 14
Thomas Formalism Dynamics: state transition graph (0 , 2) (1 , 2) vertex set S edges derived from parameter values (0 , 1) (1 , 1) ◮ corresponding component values differ at most by 1 ◮ states differ from their successors in one component only asynchronous update: sole (0 , 0) (1 , 0) assumption about time delays non-deterministic representation of the network dynamics Heike Siebert (M ATHEON / FU Berlin) Logical Modeling with Time Delays TSB 2007 4 / 14
Considering Time Delays Command to change for more than one component 2 τ 1 < τ 2 1 − − compare time delays associated with (0 , 2) (1 , 2) different processes τ 1 = τ 2 1 2 − − ◮ distinguish between components 2 τ 2 < τ 1 1 − − ◮ distinguish between production and decay processes τ 1 < τ 2 1 1 − − (0 , 1) (1 , 1) ◮ take expression levels into account allow for the possibility of time delay τ 1 = τ 2 + 0 + 0 1 1 0 + τ 2 < τ 1 0 + − − equality τ 2 < τ 1 τ 1 = τ 2 1 1 − − (0 , 0) (1 , 0) + + τ 1 < τ 2 0 0 Heike Siebert (M ATHEON / FU Berlin) Logical Modeling with Time Delays TSB 2007 5 / 14
Considering Time Delays Command to change for more than one component compare time delays associated with (0 , 2) (1 , 2) different processes ◮ distinguish between components 2 1 τ 2 < τ 1 − − ◮ distinguish between production and decay processes (0 , 1) (1 , 1) ◮ take expression levels into account allow for the possibility of time delay τ 2 + τ 2 1 2 − − 1 < τ 1 − equality complexity of time constraints may (0 , 0) (1 , 0) increase with path length Heike Siebert (M ATHEON / FU Berlin) Logical Modeling with Time Delays TSB 2007 5 / 14
Introducing Time Timed Automata [ R. Alur, D. Dill, 1994 ] clocks measure time, progress linear and synchronously clock constraints are formulated in the grammar ϕ :: = c ≤ q | c ≥ q | c < q | c > q | ϕ 1 ∧ ϕ 2 Heike Siebert (M ATHEON / FU Berlin) Logical Modeling with Time Delays TSB 2007 6 / 14
Introducing Time Timed Automata [ R. Alur, D. Dill, 1994 ] clocks measure time, progress linear and synchronously clock constraints are formulated in the grammar ϕ :: = c ≤ q | c ≥ q | c < q | c > q | ϕ 1 ∧ ϕ 2 timed automata may be visualized as digraphs where ◮ vertices (locations) represent A states ◮ edges represent (discrete) state changes B C Heike Siebert (M ATHEON / FU Berlin) Logical Modeling with Time Delays TSB 2007 6 / 14
Introducing Time Timed Automata [ R. Alur, D. Dill, 1994 ] clocks measure time, progress linear and synchronously clock constraints are formulated in the grammar ϕ :: = c ≤ q | c ≥ q | c < q | c > q | ϕ 1 ∧ ϕ 2 timed automata may be visualized as digraphs where ◮ vertices (locations) represent A c 1 ≤ q 1 states c 1 ≥ q 3 c 2 ≥ q 1 ◮ edges represent (discrete) state c 2 , c 1 ≤ q 3 c 1 := 0 changes c 1 := 0 ◮ time constraints may be posed on B C states and edges, clocks may be c 2 ≥ q 1 reset c 1 ≤ q 1 c 1 := 0 c 2 := 0 Heike Siebert (M ATHEON / FU Berlin) Logical Modeling with Time Delays TSB 2007 6 / 14
Modus Operandi 1. Model each component incorporating information on ◮ expression levels, ◮ interactions, ◮ parameter values, ◮ time delays. Heike Siebert (M ATHEON / FU Berlin) Logical Modeling with Time Delays TSB 2007 7 / 14
Modus Operandi 1. Model each component incorporating information on ◮ expression levels, ◮ interactions, ◮ parameter values, ◮ time delays. 2. Combine the components to a model supplying information on ◮ the state space of the network, ◮ state changes induced by the structure and parameter specification of the network, ◮ constraints on time delays associated with state changes. Heike Siebert (M ATHEON / FU Berlin) Logical Modeling with Time Delays TSB 2007 7 / 14
Modus Operandi 1. Model each component incorporating information on ◮ expression levels, ◮ interactions, ◮ parameter values, ◮ time delays. 2. Combine the components to a model supplying information on ◮ the state space of the network, ◮ state changes induced by the structure and parameter specification of the network, ◮ constraints on time delays associated with state changes. 3. Evaluate the data inherent in the network model to obtain a representation of the dynamical behavior in agreement with all given constraints. Heike Siebert (M ATHEON / FU Berlin) Logical Modeling with Time Delays TSB 2007 7 / 14
Modeling Each Component − , 1 + , 1 − , 2 α 1 α 2 − , 1 one clock for each component f : S → S Heike Siebert (M ATHEON / FU Berlin) Logical Modeling with Time Delays TSB 2007 8 / 14
Modeling Each Component − , 1 + , 1 − , 2 α 1 α 2 − , 1 one clock for each component f : S → S expression levels α 0 1 α 1 1 Heike Siebert (M ATHEON / FU Berlin) Logical Modeling with Time Delays TSB 2007 8 / 14
Modeling Each Component − , 1 + , 1 − , 2 α 1 α 2 − , 1 one clock for each component f : S → S expression levels – distinction between stationary states and states representing the α 0 1 process of expression level change α 0+ 1 α 1 − 1 α 1 1 Heike Siebert (M ATHEON / FU Berlin) Logical Modeling with Time Delays TSB 2007 8 / 14
Modeling Each Component − , 1 + , 1 − , 2 α 1 α 2 − , 1 one clock for each component f : S → S expression levels – distinction between stationary states and states representing the α 0 1 process of expression level change maximal and minimal time delays associated with expression level c 1 ≥ t 1 − α 0+ 1 1 change c 1 ≤ T 0+ 1 α 1 − location changes due to elapse of 1 c 1 ≤ T 1 − time 1 c 1 ≥ t 0+ 1 α 1 1 Heike Siebert (M ATHEON / FU Berlin) Logical Modeling with Time Delays TSB 2007 8 / 14
Recommend
More recommend
