LLVM IR and the IoT Dvid Juhsz david.juhasz@imsystech.com 4/2/2018 - PowerPoint PPT Presentation

A unique processor architecture meeting LLVM IR and the IoT Dávid Juhász david.juhasz@imsystech.com 4/2/2018 1 FOSDEM 2018 LLVM devroom

Compiling with LLVM High-Level Programming Language LLVM LLVM Front-end LLVM Assembly / IR LLVM Middle-end LLVM Back-end Your Typical Target ISA 4/2/2018 FOSDEM 2018 LLVM devroom 2

Improving Efficiency by Lifting Target High-Level Programming Language LLVM LLVM Front-end LLVM Assembly / IR LLVM Middle-end Imsys ISA for LLVM LLVM Back-end Your Typical Target ISA 4/2/2018 FOSDEM 2018 LLVM devroom 3

Agenda 1. Imsys Company and the IoT 2. Imsys Lean Processing Technology 3. Imsys ISA for LLVM 4/2/2018 FOSDEM 2018 LLVM devroom 4

Imsys AB Module Device IP IC 4/2/2018 FOSDEM 2018 LLVM devroom 5

Networked Embedded Controllers 4/2/2018 FOSDEM 2018 LLVM devroom 6

Imsys EMBLA Single Controller Solution for the IoT 4/2/2018 FOSDEM 2018 LLVM devroom 7

High-Level Software Platform Application Code C/C++ Java Integrated Development Environment LLVM Executable Binary 4/2/2018 FOSDEM 2018 LLVM devroom 8

Improving Efficiency by Reducing the ISA Gap High-Level Programming Language LLVM LLVM Front-end LLVM Assembly / IR LLVM Middle-end Imsys ISA for LLVM LLVM Back-end Your Typical Target ISA 4/2/2018 FOSDEM 2018 LLVM devroom 9

Abstraction Layers Application Code Assembly/C/C++ JAVA ISAL ISAJ Imsys Instruction Set Support Imsys Processor Core 4/2/2018 FOSDEM 2018 LLVM devroom 10

A Forgotten Layer of Abstraction Software Software Microcode Hardware Hardware 4/2/2018 FOSDEM 2018 LLVM devroom 11

The Processor Architect’s Best Friend Microprogram Mult . IO ALU MEM Ctrl. Addr . 4/2/2018 FOSDEM 2018 LLVM devroom 12

Minimal Complete Hardware Deterministic Maximum Control Efficiency Microcode, what is it good for? Flexibility Soft- Reconfigurability 4/2/2018 FOSDEM 2018 LLVM devroom 13

Abstraction Layers Revisited Application Code Software ISAL Imsys Instruction Set Support Microcode Imsys Processor Core Hardware 4/2/2018 FOSDEM 2018 LLVM devroom 14

A Unique Balance between Hardware and Software Application Compiler Balanced Rich ISA Domain- Microcode specific Operations Operation-Oriented Hardware Architecture Instruction Set Architecture Instruction Set Architecture 4/2/2018 FOSDEM 2018 LLVM devroom 15

Improving Efficiency by Matching LLVM Assembly High-Level Programming Language LLVM LLVM Front-end LLVM Assembly / IR LLVM Middle-end Imsys ISA for LLVM LLVM Back-end Your Typical Target ISA 4/2/2018 FOSDEM 2018 LLVM devroom 16

Matching LLVM Assembly Simple, efficient, LLVM Assembly general LLVM LLVM back-end LLVM for ISAL middle-end Direct use of Semantically optimizations ISAL matching instructions 4/2/2018 FOSDEM 2018 LLVM devroom 17

Meeting a Constrained Reality LLVM Assembly ISAL Operations Instructions & Additional system operations intrinsic functions Single Value Types Virtually unlimited Set of integer, floating point, pointer, and vector types Registers Unlimited Register windows Arguments Source and Registers with support of destination registers accumulating in source registers, immediate values Binary Representation Bitcode Custom dense binary coding 4/2/2018 FOSDEM 2018 LLVM devroom 19

Optimized Operation Sequences a ≔ a + b Accumulating in source register add a a b opcode dst src1 src2 add.upd a b opcode src1 src2 a ≔ a + 42 Immediate values add.imm a a 42 move b 42 add a a b add.upd.imm a 42 4/2/2018 FOSDEM 2018 LLVM devroom 20

Optimized Binary Representation Maximize Code Density 1 2 3 4 5 6 7 8 9 10 500 465 450 Number of Instructions Optimize 400 Microcode Size 350 300 258 250 198 200 161 150 Minimize 100 Execution Time 50 7 11 0 0 0 1 4 Variable-length Intstruction Lengths (Bytes) Instructions 4/2/2018 FOSDEM 2018 LLVM devroom 21

Average Binary Size of TI Suite 2,5 2 1,5 1 0,5 0 Imsys Cortex-M0+ Cortex-M4 x86 x64 ARM Cortex requires 35%+ more, Intel 80%+ more program memory. 4/2/2018 FOSDEM 2018 LLVM devroom 22

LLVM Assembly Imsys ISA LLVM back-end for ISAL for LLVM ISAL Imsys Firmware Imsys Processor Core Imsys Lean Processing Technology Dávid Juhász david.juhasz@imsystech.com Leaner is Meaner 4/2/2018 FOSDEM 2018 LLVM devroom 23