lecture 3 model checker nusmv
play

Lecture 3: Model-checker NuSMV B. Srivathsan Chennai Mathematical - PowerPoint PPT Presentation

Oct 06, 2022 •592 likes •1.72k views

Lecture 3: Model-checker NuSMV B. Srivathsan Chennai Mathematical Institute NPTEL-course July - November 2015 1 / 31 Model-checker Specify the model of the system Specify the requirements Model-checker will automatically check if system

  1. � × × request=0 request=1 request=0 G (request=0) ready ready ready request=1 request=1 ready busy request=0 request=1 request=0 busy busy ready request=0 request=0 request=0 ... request=0 request=0 ready busy ready ready ready request=1 request=1 request=0 busy busy ready TS does not satisfy G (request=0) request=1 request=0 request=0 busy ready ready . . . . . . . . . 13 / 31

  2. Execution satisfies G (expr) if expr evaluates to T in all its states ... T T T T T T 14 / 31

  3. Execution satisfies G (expr) if expr evaluates to T in all its states ... T T T T T T Transition system satisfies G (expr) if all its executions satisfy G (expr) 14 / 31

  4. Checking the G requirement: NuSMV demo 15 / 31

  5. Requirement type 2: F 16 / 31

  6. Requirement type 2: F l 1 , x=0 F ( x >= 5 ) l 1 l 2 , x=0 l 1 , x=1 x := x+1 x < 10 l 2 l 2 , x=1 . . . l 1 , x=9 l 2 , x=9 l 1 , x=10 16 / 31

  7. Requirement type 2: F l 1 , x=0 F ( x >= 5 ) l 1 l 2 , x=0 l 1 , x=1 x := x+1 x < 10 l 2 l 2 , x=1 . . . TS of above PG with initial value x=0 satisfies F ( x >= 5 ) l 1 , x=9 l 2 , x=9 l 1 , x=10 16 / 31

  8. request=0 request=1 request=0 F (request=1) ready ready ready request=1 request=1 ready busy request=0 request=1 request=0 busy busy ready request=0 request=0 request=0 ... request=0 request=0 ready busy ready ready ready request=1 request=1 request=0 busy busy ready request=1 request=0 request=0 busy ready ready . . . . . . . . . 17 / 31

  9. � request=0 request=1 request=0 F (request=1) ready ready ready request=1 request=1 ready busy request=0 request=1 request=0 busy busy ready request=0 request=0 request=0 ... request=0 request=0 ready busy ready ready ready request=1 request=1 request=0 busy busy ready request=1 request=0 request=0 busy ready ready . . . . . . . . . 17 / 31

  10. � � request=0 request=1 request=0 F (request=1) ready ready ready request=1 request=1 ready busy request=0 request=1 request=0 busy busy ready request=0 request=0 request=0 ... request=0 request=0 ready busy ready ready ready request=1 request=1 request=0 busy busy ready request=1 request=0 request=0 busy ready ready . . . . . . . . . 17 / 31

  11. � � × request=0 request=1 request=0 F (request=1) ready ready ready request=1 request=1 ready busy request=0 request=1 request=0 busy busy ready request=0 request=0 request=0 ... request=0 request=0 ready busy ready ready ready request=1 request=1 request=0 busy busy ready request=1 request=0 request=0 busy ready ready . . . . . . . . . 17 / 31

  12. � � × request=0 request=1 request=0 F (request=1) ready ready ready request=1 request=1 ready busy request=0 request=1 request=0 busy busy ready request=0 request=0 request=0 ... request=0 request=0 ready busy ready ready ready request=1 request=1 request=0 busy busy ready TS does not satisfy F (request=1) request=1 request=0 request=0 busy ready ready . . . . . . . . . 17 / 31

  13. Execution satisfies F (expr) if expr evaluates to T in one of its states ... T 18 / 31

  14. Execution satisfies F (expr) if expr evaluates to T in one of its states ... T Transition system satisfies F (expr) if all its executions satisfy F (expr) 18 / 31

  15. Checking the F requirement: NuSMV demo 19 / 31

  16. Coming next: Combining G and F 20 / 31

  17. request=0 request=1 request=0 G ( request=1 => F status=busy ) ready ready ready request=1 request=1 ready busy request=0 request=1 request=0 busy busy ready request=0 request=0 request=0 request=0 request=0 ready busy ready ready ready request=1 request=1 request=0 busy busy ready request=1 request=0 request=0 busy ready ready . . . . . . . . . 21 / 31

  18. � request=0 request=1 request=0 G ( request=1 => F status=busy ) ready ready ready request=1 request=1 ready busy request=0 request=1 request=0 busy busy ready request=0 request=0 request=0 request=0 request=0 ready busy ready ready ready request=1 request=1 request=0 busy busy ready request=1 request=0 request=0 busy ready ready . . . . . . . . . 21 / 31

  19. � � request=0 request=1 request=0 G ( request=1 => F status=busy ) ready ready ready request=1 request=1 ready busy request=0 request=1 request=0 busy busy ready request=0 request=0 request=0 request=0 request=0 ready busy ready ready ready request=1 request=1 request=0 busy busy ready request=1 request=0 request=0 busy ready ready . . . . . . . . . 21 / 31

  20. � � � request=0 request=1 request=0 G ( request=1 => F status=busy ) ready ready ready request=1 request=1 ready busy request=0 request=1 request=0 busy busy ready request=0 request=0 request=0 request=0 request=0 ready busy ready ready ready request=1 request=1 request=0 busy busy ready request=1 request=0 request=0 busy ready ready . . . . . . . . . 21 / 31

  21. � � � request=0 request=1 request=0 G ( request=1 => F status=busy ) ready ready ready request=1 request=1 ready busy request=0 request=1 request=0 busy busy ready request=0 request=0 request=0 request=0 request=0 ready busy ready ready ready request=1 request=1 request=0 busy busy ready TS satisfies G ( request => F (status=busy) ) request=1 request=0 request=0 busy ready ready . . . . . . . . . 21 / 31

  22. Summary Using NuSMV Format for writing models G and F requirements 22 / 31

  23. Summary Using NuSMV Format for writing models G and F requirements Coming next: More circuits 22 / 31

  24. in 1 NAND out in 2 23 / 31

  25. in 1 NAND out in 2 MODULE main VAR in1: boolean; in2: boolean; DEFINE −− ZERO DELAY out := !(in1 & in2); 23 / 31

  26. in 1 NAND out in 2 MODULE main VAR in1: boolean; in2: boolean; 0 0 0 1 DEFINE 1 1 −− ZERO DELAY out := !(in1 & in2); 1 1 0 1 1 0 23 / 31

  27. in 1 NAND out in 2 MODULE main VAR in1: boolean; in2: boolean; 0 0 0 1 DEFINE 1 1 −− ZERO DELAY out := !(in1 & in2); 1 1 0 1 1 0 23 / 31

  28. in 1 NAND out in 2 MODULE main VAR in1: boolean; in2: boolean; 0 0 0 1 DEFINE 1 1 −− ZERO DELAY out := !(in1 & in2); 1 1 0 1 1 0 23 / 31

  29. in 1 NAND out in 2 MODULE main VAR in1: boolean; in2: boolean; out: boolean; ASSIGN −− UNIT DELAY init(out) := TRUE; next(out) := !(in1 & in2); 24 / 31

  30. in 1 NAND out in 2 MODULE main VAR 0 0 in1: boolean; 0 0 0 1 in2: boolean; out: boolean; 0 0 ASSIGN 1 1 0 1 −− UNIT DELAY init(out) := TRUE; 1 1 next(out) := !(in1 & in2); 0 0 0 1 1 1 1 1 0 1 24 / 31

  31. in 1 NAND out in 2 MODULE main VAR 0 0 in1: boolean; 0 0 0 1 in2: boolean; out: boolean; 0 0 ASSIGN 1 1 0 1 −− UNIT DELAY init(out) := TRUE; 1 1 next(out) := !(in1 & in2); 0 0 0 1 1 1 1 1 0 1 24 / 31

  32. in 1 NAND out in 2 MODULE main VAR 0 0 in1: boolean; 0 0 0 1 in2: boolean; out: boolean; 0 0 ASSIGN 1 1 0 1 −− UNIT DELAY init(out) := TRUE; 1 1 next(out) := !(in1 & in2); 0 0 0 1 1 1 1 1 0 1 24 / 31

  33. in 1 NAND out in 2 MODULE main VAR 0 0 in1: boolean; 0 0 0 1 in2: boolean; out: boolean; 0 0 ASSIGN 1 1 0 1 −− UNIT DELAY init(out) := TRUE; 1 1 next(out) := !(in1 & in2); 0 0 0 1 1 1 1 1 0 1 24 / 31

  34. in 1 NAND out in 2 MODULE main VAR 0 0 in1: boolean; 0 0 0 1 in2: boolean; out: boolean; 0 0 ASSIGN 1 1 0 1 −− UNIT DELAY init(out) := TRUE; 1 1 next(out) := !(in1 & in2); 0 0 0 1 1 1 1 1 0 1 24 / 31

  35. in 1 NAND out MODULE main in 2 VAR input1: boolean; input2: boolean; 0 0 q: nand2(input1, input2); 0 0 0 1 MODULE nand2(in1, in2) 0 0 VAR 1 1 0 1 out: boolean; ASSIGN 1 1 −− UNIT DELAY 0 0 0 1 init(out) := TRUE; next(out) := !(in1 & in2); 1 1 1 1 0 1 25 / 31

  36. MODULE main VAR x1: boolean; x2:boolean; y1: boolean; y2:boolean; q1: nand2(x1, x2); x 1 q2: nand2(y1, y2); NAND x 2 DEFINE XOR −− ZERO DELAY fout := q1.out xor q2.out; y 1 NAND y 2 MODULE nand2(in1, in2) VAR out: boolean; ASSIGN −− UNIT DELAY init(out) := TRUE; next(out) := !(in1 & in2); 26 / 31

  37. MODULE main VAR x: boolean; y: boolean; q1: nand2(x, q2.out); x q2: nand2(q1.out, y); NAND DEFINE XOR −− ZERO DELAY fout := q1.out xor q2.out; NAND y MODULE nand2(in1, in2) VAR out: boolean ASSIGN −− UNIT DELAY init(out) := TRUE; next(out) := !(in1 & in2); 27 / 31

  38. Coming next: Three-bit adder 28 / 31

  39. MODULE counter_cell(carry_in) VAR value:boolean; ASSIGN init(value):=FALSE; next(value):= value xor carry_in; DEFINE carry_out := carry_in & value; MODULE main VAR bit0:counter_cell(TRUE); bit1:counter_cell(bit0.carry_out); bit2:counter_cell(bit1.carry_out); 29 / 31

  40. bit2 bit1 bit0 carry_in 0 0 1 MODULE counter_cell(carry_in) value 0 0 0 0 0 0 carry_out VAR value:boolean; ASSIGN init(value):=FALSE; next(value):= value xor carry_in; DEFINE carry_out := carry_in & value; MODULE main VAR bit0:counter_cell(TRUE); bit1:counter_cell(bit0.carry_out); bit2:counter_cell(bit1.carry_out); 29 / 31

  41. bit2 bit1 bit0 carry_in 0 0 1 MODULE counter_cell(carry_in) value 0 0 0 0 0 0 carry_out VAR value:boolean; 1 ASSIGN init(value):=FALSE; next(value):= value xor carry_in; DEFINE carry_out := carry_in & value; MODULE main VAR bit0:counter_cell(TRUE); bit1:counter_cell(bit0.carry_out); bit2:counter_cell(bit1.carry_out); 29 / 31

  42. bit2 bit1 bit0 carry_in 0 0 1 MODULE counter_cell(carry_in) value 0 0 0 0 0 0 carry_out VAR 1 value:boolean; 1 ASSIGN init(value):=FALSE; next(value):= value xor carry_in; DEFINE carry_out := carry_in & value; MODULE main VAR bit0:counter_cell(TRUE); bit1:counter_cell(bit0.carry_out); bit2:counter_cell(bit1.carry_out); 29 / 31

  43. bit2 bit1 bit0 carry_in 0 0 1 MODULE counter_cell(carry_in) value 0 0 0 0 0 0 carry_out VAR 1 value:boolean; 1 1 ASSIGN init(value):=FALSE; next(value):= value xor carry_in; DEFINE carry_out := carry_in & value; MODULE main VAR bit0:counter_cell(TRUE); bit1:counter_cell(bit0.carry_out); bit2:counter_cell(bit1.carry_out); 29 / 31

  44. bit2 bit1 bit0 carry_in 0 0 1 MODULE counter_cell(carry_in) value 0 0 0 0 0 0 carry_out VAR 1 value:boolean; 0 1 1 ASSIGN init(value):=FALSE; next(value):= value xor carry_in; DEFINE carry_out := carry_in & value; MODULE main VAR bit0:counter_cell(TRUE); bit1:counter_cell(bit0.carry_out); bit2:counter_cell(bit1.carry_out); 29 / 31

  45. bit2 bit1 bit0 carry_in 0 0 1 MODULE counter_cell(carry_in) value 0 0 0 0 0 0 carry_out VAR 1 1 value:boolean; 0 1 1 ASSIGN init(value):=FALSE; next(value):= value xor carry_in; DEFINE carry_out := carry_in & value; MODULE main VAR bit0:counter_cell(TRUE); bit1:counter_cell(bit0.carry_out); bit2:counter_cell(bit1.carry_out); 29 / 31

  46. bit2 bit1 bit0 carry_in 0 0 1 MODULE counter_cell(carry_in) value 0 0 0 0 0 0 carry_out VAR 1 1 value:boolean; 0 0 1 1 ASSIGN init(value):=FALSE; next(value):= value xor carry_in; DEFINE carry_out := carry_in & value; MODULE main VAR bit0:counter_cell(TRUE); bit1:counter_cell(bit0.carry_out); bit2:counter_cell(bit1.carry_out); 29 / 31

  47. bit2 bit1 bit0 carry_in 0 0 1 MODULE counter_cell(carry_in) value 0 0 0 0 0 0 carry_out VAR 0 1 1 value:boolean; 0 0 0 0 1 1 ASSIGN init(value):=FALSE; next(value):= value xor carry_in; DEFINE carry_out := carry_in & value; MODULE main VAR bit0:counter_cell(TRUE); bit1:counter_cell(bit0.carry_out); bit2:counter_cell(bit1.carry_out); 29 / 31

  48. bit2 bit1 bit0 carry_in 0 0 1 MODULE counter_cell(carry_in) value 0 0 0 0 0 0 carry_out VAR 0 1 1 value:boolean; 0 0 0 0 1 1 ASSIGN init(value):=FALSE; 0 next(value):= value xor carry_in; DEFINE carry_out := carry_in & value; MODULE main VAR bit0:counter_cell(TRUE); bit1:counter_cell(bit0.carry_out); bit2:counter_cell(bit1.carry_out); 29 / 31

  49. bit2 bit1 bit0 carry_in 0 0 1 MODULE counter_cell(carry_in) value 0 0 0 0 0 0 carry_out VAR 0 1 1 value:boolean; 0 0 0 0 1 1 ASSIGN 1 init(value):=FALSE; 0 next(value):= value xor carry_in; DEFINE carry_out := carry_in & value; MODULE main VAR bit0:counter_cell(TRUE); bit1:counter_cell(bit0.carry_out); bit2:counter_cell(bit1.carry_out); 29 / 31

  50. bit2 bit1 bit0 carry_in 0 0 1 MODULE counter_cell(carry_in) value 0 0 0 0 0 0 carry_out VAR 0 1 1 value:boolean; 0 0 0 0 1 1 ASSIGN 1 init(value):=FALSE; 0 0 next(value):= value xor carry_in; DEFINE carry_out := carry_in & value; MODULE main VAR bit0:counter_cell(TRUE); bit1:counter_cell(bit0.carry_out); bit2:counter_cell(bit1.carry_out); 29 / 31

  51. bit2 bit1 bit0 carry_in 0 0 1 MODULE counter_cell(carry_in) value 0 0 0 0 0 0 carry_out VAR 0 1 1 value:boolean; 0 0 0 0 1 1 ASSIGN 1 init(value):=FALSE; 1 0 0 next(value):= value xor carry_in; DEFINE carry_out := carry_in & value; MODULE main VAR bit0:counter_cell(TRUE); bit1:counter_cell(bit0.carry_out); bit2:counter_cell(bit1.carry_out); 29 / 31

  52. bit2 bit1 bit0 carry_in 0 0 1 MODULE counter_cell(carry_in) value 0 0 0 0 0 0 carry_out VAR 0 1 1 value:boolean; 0 0 0 0 1 1 ASSIGN 0 1 init(value):=FALSE; 1 0 0 next(value):= value xor carry_in; DEFINE carry_out := carry_in & value; MODULE main VAR bit0:counter_cell(TRUE); bit1:counter_cell(bit0.carry_out); bit2:counter_cell(bit1.carry_out); 29 / 31

  53. bit2 bit1 bit0 carry_in 0 0 1 MODULE counter_cell(carry_in) value 0 0 0 0 0 0 carry_out VAR 0 1 1 value:boolean; 0 0 0 0 1 1 ASSIGN 0 1 init(value):=FALSE; 0 1 0 0 next(value):= value xor carry_in; DEFINE carry_out := carry_in & value; MODULE main VAR bit0:counter_cell(TRUE); bit1:counter_cell(bit0.carry_out); bit2:counter_cell(bit1.carry_out); 29 / 31

  54. bit2 bit1 bit0 carry_in 0 0 1 MODULE counter_cell(carry_in) value 0 0 0 0 0 0 carry_out VAR 0 1 1 value:boolean; 0 0 0 0 1 1 ASSIGN 0 0 1 init(value):=FALSE; 0 0 0 1 0 0 next(value):= value xor carry_in; DEFINE carry_out := carry_in & value; MODULE main VAR bit0:counter_cell(TRUE); bit1:counter_cell(bit0.carry_out); bit2:counter_cell(bit1.carry_out); 29 / 31

  55. bit2 bit1 bit0 carry_in 0 0 1 MODULE counter_cell(carry_in) value 0 0 0 0 0 0 carry_out VAR 0 1 1 value:boolean; 0 0 0 0 1 1 ASSIGN 0 0 1 init(value):=FALSE; 0 0 0 1 0 0 next(value):= value xor carry_in; 1 1 1 DEFINE 0 0 1 1 1 1 carry_out := carry_in & value; MODULE main VAR bit0:counter_cell(TRUE); bit1:counter_cell(bit0.carry_out); bit2:counter_cell(bit1.carry_out); 29 / 31

Recommend

Hoare Logic and Model Checking Model Checking See NuSMV homepage to download: http://nusmv.fbk.eu/

Hoare Logic and Model Checking Model Checking See NuSMV homepage to download: http://nusmv.fbk.eu/

Hoare Logic and Model Checking Model Checking See NuSMV homepage to download: http://nusmv.fbk.eu/ Was popular in semiconductor industry via Cadence SMV Could handle large models A re-implementation of the SMV model checker: Good

110 views • 10 slides
Automated Reasoning Lecture 3: Tie NuSMV Model Checler Jacques Fleuriot jdf@inf.ed.ac.uk Recap

Automated Reasoning Lecture 3: Tie NuSMV Model Checler Jacques Fleuriot jdf@inf.ed.ac.uk Recap

Automated Reasoning Lecture 3: Tie NuSMV Model Checler Jacques Fleuriot jdf@inf.ed.ac.uk Recap Previously: Model Checking Introduction Linear Temporal Logic Tiis time: An implementation of LTL Model Checking NuSMV NuSMV

442 views • 23 slides
Model Checker NuSMV Hao Zheng Department of Computer Science and Engineering University of South

Model Checker NuSMV Hao Zheng Department of Computer Science and Engineering University of South

Model Checker NuSMV Hao Zheng Department of Computer Science and Engineering University of South Florida Tampa, FL 33620 Email: zheng@cse.usf.edu Phone: (813)974-4757 Fax: (813)974-5456 Hao Zheng (CSE, USF) Comp Sys Verification 1 / 35

618 views • 46 slides
Lecture 5. Symbolic model checking. NuSMV and SPIN model checkers. User-friendly model checking

Lecture 5. Symbolic model checking. NuSMV and SPIN model checkers. User-friendly model checking

Lecture 5. Symbolic model checking. NuSMV and SPIN model checkers. User-friendly model checking ELEC-E8110 Automation Systems Synthesis and Analysis Igor Buzhinsky igor.buzhinskii@aalto.fi 2018 Igor Buzhinsky Lecture 5 2018 1 / 28 Symbolic

833 views • 61 slides
Lecture 4: Checking properties in NuSMV B. Srivathsan Chennai Mathematical Institute Model

Lecture 4: Checking properties in NuSMV B. Srivathsan Chennai Mathematical Institute Model

Lecture 4: Checking properties in NuSMV B. Srivathsan Chennai Mathematical Institute Model Checking and Systems Verification January - April 2016 1 / 43 Outline Module 1: Synchronous Vs Asynchronous composition Module 2: More examples

1.11k views • 90 slides
Hoare Logic and Model Checking 1. You should be able to model simple systems in NuSMV, an LTL

Hoare Logic and Model Checking 1. You should be able to model simple systems in NuSMV, an LTL

Hoare Logic and Model Checking 1. You should be able to model simple systems in NuSMV, an LTL Other interesting books: Model Checking by Clarke, Grumberg, and Peled Principles of Model Checking by Baier and Katoen 3 Course

636 views • 11 slides
The UPPAAL Model Checker The UPPAAL Model Checker Julin Proenza Systems, Robotics and Vision

The UPPAAL Model Checker The UPPAAL Model Checker Julin Proenza Systems, Robotics and Vision

The UPPAAL Model Checker The UPPAAL Model Checker Julin Proenza Systems, Robotics and Vision Group. UIB. SPAIN Julin Proenza. UIB. Oct 2008 The aim of this presentation Introduce the basic concepts of model checking from a practical

804 views • 68 slides
NuSMV and Symbolic Model Checking A. Cimatti, M. Pistore, and M. Roveri NuSMV Project Sep 1,

NuSMV and Symbolic Model Checking A. Cimatti, M. Pistore, and M. Roveri NuSMV Project Sep 1,

NuSMV and Symbolic Model Checking A. Cimatti, M. Pistore, and M. Roveri NuSMV and Symbolic Model Checking A. Cimatti, M. Pistore, and M. Roveri NuSMV Project Sep 1, 2002 Trento (Italy) NuSMV Project, Sep 1, 2002, Trento (Italy) 1

1.24k views • 105 slides
Implementation of a Coalgebraic Model Checker Aaron Strahlberger 16.07.2019 Parity Game based

Implementation of a Coalgebraic Model Checker Aaron Strahlberger 16.07.2019 Parity Game based

Implementation of a Coalgebraic Model Checker Aaron Strahlberger 16.07.2019 Parity Game based Model Checker Game-Based Local Model Checking for the Coalgebraic -Calculus by Daniel Hausmann and Lutz Schrder [1] (CONCUR 2019)

474 views • 31 slides
Verification of a Dynamic Channel Model using the SPIN Model Checker Rune M. Friborg and Brian

Verification of a Dynamic Channel Model using the SPIN Model Checker Rune M. Friborg and Brian

Verification of a Dynamic Channel Model using the SPIN Model Checker Rune M. Friborg and Brian Vinter eScience center, University of Copenhagen Dias 1 Introduction to PyCSP 2007 - PyCSP is presented. The synchronization model for channel

574 views • 20 slides
A Model Checker Collection for the Model Checking Contest @ Petri Nets Didier Buchs Stefan

A Model Checker Collection for the Model Checking Contest @ Petri Nets Didier Buchs Stefan

A Model Checker Collection for the Model Checking Contest @ Petri Nets Didier Buchs Stefan Klikovits Alban Linard Romain Mencattini Dimitri Racordon 28 June 2018 1/11 1/11 Examination Result GreatSPN ITSTools LoLA LTSMin Marcie

613 views • 20 slides
Schedulability Analysis of Timed CSP Models Using the PAT Model Checker O uzcan O UZ Jan

Schedulability Analysis of Timed CSP Models Using the PAT Model Checker O uzcan O UZ Jan

Schedulability Analysis of Timed CSP Models Using the PAT Model Checker O uzcan O UZ Jan F. BROENINK Angelika MADER Robotics and Mechatronics, University of Twente, The Netherlands Contents Problem Statement &amp; Approach

516 views • 24 slides
The Low-Level Bounded Model Checker LLBMC A Precise Memory Model for LLBMC Florian Merz | October

The Low-Level Bounded Model Checker LLBMC A Precise Memory Model for LLBMC Florian Merz | October

The Low-Level Bounded Model Checker LLBMC A Precise Memory Model for LLBMC Florian Merz | October 7, 2010 Carsten Sinz Stephan Falke V ERIFICATION MEETS A LGORITHM E NGINEERING www.kit.edu KIT University of the State of Baden-Wuerttemberg

415 views • 19 slides
Can a Model Checker Generate Tests for Non-Deterministic Systems? Sergiy Boroday, Alexandre

Can a Model Checker Generate Tests for Non-Deterministic Systems? Sergiy Boroday, Alexandre

Can a Model Checker Generate Tests for Non-Deterministic Systems? Sergiy Boroday, Alexandre Petrenko CRIM, Montreal, Canada Roland Groz INPG, France MBT 2007 Outline Motivation Weak and Strong Tests Test Generation Model

802 views • 22 slides
The Software Model Checker BLAST: Applications to Software Engineering Dirk Beyer, Thomas A.

The Software Model Checker BLAST: Applications to Software Engineering Dirk Beyer, Thomas A.

The Software Model Checker BLAST: Applications to Software Engineering Dirk Beyer, Thomas A. Henzinger, Ranjit Jhala, Rupak Majumdar Int. Journal on Software Tools for Technology Transfer, 2007 Stefan Buchholz March 17, 2009 1 Model

456 views • 12 slides
Towards a model-checker for counter systems S. Demri 1 A. Finkel 1 V. Goranko 2 G. van Drimmelen 2

Towards a model-checker for counter systems S. Demri 1 A. Finkel 1 V. Goranko 2 G. van Drimmelen 2

Towards a model-checker for counter systems S. Demri 1 A. Finkel 1 V. Goranko 2 G. van Drimmelen 2 1 LSV, CNRS &amp; ENS Cachan &amp; INRIA Futurs 2 University of Witwatersrand, Johannesburg ATVA, October 2006, Beijing Motivations Presburger

679 views • 37 slides
Static verification framework for Go Overview 2 Model checking Behavioural mCRL2 model checker

Static verification framework for Go Overview 2 Model checking Behavioural mCRL2 model checker

Concurrency in Go Behavioural type inference Model checking behavioural types Termination checking Summary Static verification framework for Go Overview 2 Model checking Behavioural mCRL2 model checker Types Transform Check safety and

681 views • 67 slides
A Tutorial on Model Checker SPIN Instructor: Hao Zheng Department of Computer Science and

A Tutorial on Model Checker SPIN Instructor: Hao Zheng Department of Computer Science and

A Tutorial on Model Checker SPIN Instructor: Hao Zheng Department of Computer Science and Engineering University of South Florida Tampa, FL 33620 Email: haozheng@usf.edu Phone: (813)974-4757 Fax: (813)974-5456 1 Overview of Concurrent

1.5k views • 68 slides
A Storm is Coming! A New Probabilistic Model Checker Joost-Pieter Katoen IFIP WG 1.8 Open

A Storm is Coming! A New Probabilistic Model Checker Joost-Pieter Katoen IFIP WG 1.8 Open

A Storm is Coming! A New Probabilistic Model Checker Joost-Pieter Katoen IFIP WG 1.8 Open Problems in Concurrency Theory, June 26, 2017 joint with: Christian Dehnert, Sebastian Junges and Matthias Volk Probabilistic Model Checking Theory in

468 views • 28 slides
The CBMC bounded model checker for C Paul Jackson School of Informatics University of Edinburgh

The CBMC bounded model checker for C Paul Jackson School of Informatics University of Edinburgh

The CBMC bounded model checker for C Paul Jackson School of Informatics University of Edinburgh Formal Verification Spring 2017 Sources CBMC: Bounded Model Checking for ANSI-C Introductory slides on CBMC from CProver website. V1.0, 2010.

500 views • 5 slides
A Prototype Embedding of Bluespec SystemVerilog in the SAL Model Checker Dominic Richards and

A Prototype Embedding of Bluespec SystemVerilog in the SAL Model Checker Dominic Richards and

A Prototype Embedding of Bluespec SystemVerilog in the SAL Model Checker Dominic Richards and David Lester Advanced Processor Technologies Group The University of Manchester Introduction Bluespec SystemVerilog (BSV) is a language for high

856 views • 29 slides
Benchmarking a Model Checker for Algorithmic Improvements and Tuning for Performance G. Cabodi

Benchmarking a Model Checker for Algorithmic Improvements and Tuning for Performance G. Cabodi

Benchmarking a Model Checker for Algorithmic Improvements and Tuning for Performance G. Cabodi S.Nocco S.Quer Politecnico di Torino Torino, Italy Gianpiero Cabodi - HWVW2010 1 Outline The PdTRAV tool Motivations &amp;

450 views • 26 slides
Implementing and Evaluating a Model Checker for TM Systems Woongki Baek, Nathan Bronson,

Implementing and Evaluating a Model Checker for TM Systems Woongki Baek, Nathan Bronson,

Implementing and Evaluating a Model Checker for TM Systems Woongki Baek, Nathan Bronson, Christos Kozyrakis, Kunle Olukotun wkbaek@stanford.edu Stanford University Introduction Transactional Memory (TM) simplifies parallel programming

357 views • 22 slides
Nuspell: version 3 of the new spell checker FOSS spell checker implemented in C++17 with aid of

Nuspell: version 3 of the new spell checker FOSS spell checker implemented in C++17 with aid of

Nuspell: version 3 of the new spell checker FOSS spell checker implemented in C++17 with aid of Mozilla Sander van Geloven FOSDEM, Brussels February 1, 2020 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

611 views • 39 slides

More recommend