Layout Technique for Double-Gate Silicon Nanowire FET with an - PowerPoint PPT Presentation

Layout Technique for Double-Gate Silicon Nanowire FET with an Efficient Sea-of-Tiles Architecture Shashikanth Bobba Prof. Giovanni De Micheli March 25, 2013 Pierre-Emmanuel, Jian Zhang, Luca, Michele, Davide, Prof. Yusuf Leblebici

Functionally Enhanced Device 10nm 32nm 16nm Source Gate Source Drain Gate Gate Source Drain Drain Vertically stacked SiNW FET High-K Metal Gate Tri-gate aka FinFET Enhanced S CG D Control gate Functionality Source Source Drain PG Polarity gate

Double-gate Silicon Nanowire FET S CG D S CG Control gate p-FET Source S D Drain CG Polarity gate PG PG D S CG D n-FET ! Dynamic control on the polarity of the device ! Promising feature for future reconfigurable circuits ! Ambipolar logic circuits

Ambipolar Logic Circuits ! Circuits based on double gate ambipolar transistors with controllable polarity (CNFET, SiNW FET, Graphene, …) ! Optimal for XOR and XNOR dominated circuits CNT-DR8F XOR2 ULM (5,3) K. Mohanram, DAC 12 Only 4 transistors O’Connor, ICECS 07 M-H. Ben Jamaa, PhD Thesis

Motivation XOR2 ?? Fewer transistors for XOR operation Every transistor has two gates to route �

Physical Design Challenges Arithmetic Reconfigurable Universal logic S circuits blocks modules CG PG D Design and Architecture ! Can we use existing layout Logic E techniques? Verification Synthesis D Physical DFM A ! Logic bricks for improved Yield Synthesis Manufacturing Graphene CNFET SiNW FET MoS 2

Outline ! Introduction ! Layout Technique for DG-SiNW FET " Motivation " Layout algorithm for XOR embedded Boolean functions ! Sea-of-Tiles ! Simulation Results ! Conclusion

Symbolic layouts : Dumbell-stick diagrams ! Need for new symbolic layouts for ambipolar circuits Control gate Source Drain !"#$%&%'(") Polarity gate *#&"&$+) !"#$%"&'()$*+' ,"##*,$*-'$"(*$.*%' !"#$%&&'()*+,, !"#$%&%'(") +"(,*&$+) /"&)%0$1'()$*+' ,"##*,$*-'$"(*$.*%'

Layout technique for Unate logic functions ! Negative Unate functions: NAND, NOR, AOI, OAI ! Polarity gates are biased to either Vdd or Gnd -'./0"1,232!,451%, Gnd t 2 t 1 A A t 1 t 2 t 1 t 2 B B Gnd Out Out Gnd B B t 3 t 3 Vdd t 4 t 3 A A t 4 t 4 Vdd Vdd -$./)($0)*(.#"&'/)+#'0) 6,780..9%:;<) 1(")234)#$5)264 ) 5&#+"#7 )

Layout technique for Binate logic functions t 2 t 1 ?(7*.0C)"(,:$+ ) 678,451%, ?@-=)%'/.0) .#/(,' ) t 2 t 1 B t 3 t 4 A A B Y t 3 t 4 B !"#$%&%'(")+"(,*&$+ ) A A B 4(A0.) t 2 t 4 #**"(#;B ) =&7*.&>05)"(,:$+ ) t 1 t 3

Complex gates with embedded XOR/XNOR F1 = (A + B)(C + D) #D !"#$%&%'(")+"(,*&$+)) group D : { t 3 , t 5 } A t 1 t 3 D 8D))))!"#$%&%'(")*#&"&$+) group D : { t 4 , t 6 } C C Gnd t 4 ;D))))!"#$%&%'(")("50"&$+) D group Vdd : { t 7 , t 8 } t 2 B 5D))))!"#$%&%'(");B#&$&$+) group Gnd : { t 1 , t 2 } Gnd F1 t 5 D C C t 6 D Vdd t 7 A B t 8 Vdd ))))))6,780..9%:;<)5&#+"#7 )

Layout Extraction !"#$%&%'(")%&E&$+)F)G#/(,')+0$0"#:($ ) 6,780..9%:;<)5&#+"#7 ) VDD GND

Outline ! Introduction ! Layout Technique for DG-SiNW FET ! Sea-of-Tiles " Tiles as basic blocks " Optimal Tile " Power distribution for SoT ! Simulation Results ! Conclusion

Sea-of-Tiles (SoT)

Layout regularity with Tiles 9.&%, !H()'"#$%&%'(")*#&"%) +"(,*05)'(+0'B0" ) 678-, 232!-,

Sea-of-Tiles (SoT) ! Gate to Tile mapping :51%(, /;, /-, /<, /=, />, /?, :;, :-, 4;, 4-, 6@A-, I$5) -,') J55) I$5) -,') J55) K) KL) ML) M) 6/@A-, I$5) -,') J55) I$5) -,') J55) K) KL) M) ML) 25/B-, -,') J55) -,') -,') 9) I$5) K) M) I$5) J55) 2@A-, J55) 9) -,') -,') I$5) -,') K) M) I$5) J55) C/D-6, J55) -,') J55) I$5) -,') I$5) K) K) I$5) J55) E"F, -N) J55) -O) -O) I$5) -N) K) -N) I$5) J55)

Various logic Tiles as basic building blocks 3 9.&% :;, 9.&% :;G-, 2314%0-'50&*6 ' 9.&% :-, 9.&% :<,

Design flow for determining the Optimal Tile Benchmark Circuits Generate Tiles Physical Synopsys Design Synthesis onto Compiler Area Library of Tiles Sea-of-Tiles TECHNOLOGY MAPPING

Design flow for determining the Optimal Tile Benchmark Circuits Generate Tiles Physical Synopsys Design Synthesis onto Compiler Area Library of Tiles Sea-of-Tiles TECHNOLOGY MAPPING Tile G2 #2 Tile G2 #1 + + P A K ? M + P P + A A Unmapped active area

Result: Impact on Area Area across various benchmarks 2@A#5&.H%B,3A%5 , - 14% - 16% 9.&% :;G-, 9.&% :<, 9.&% :-, 9.&% :;, ! Tile G2 and Tile G1h2 optimal for mapping logic gates, with respect to reduced routing complexity thereby reducing in the overall active area

Sea-of-Tiles Power Distribution… VDD XOR NAND GND NAND2 XOR2 A B Gnd Y Too much requirements B Vdd in wiring VDD A Vdd GND Source: S. Bobba et al , NANOARCH’12

Sea-of-Tiles Power Distribution GND VDD GND GND Lower wiring requirements GND VDD VDD GND VDD VDD GND Source: S. Bobba et al , NANOARCH’12

Outline ! Introduction ! Layout Technique for DG-SiNW FET ! Sea-of-Tiles ! Simulation Results " Arithmetic Circuits " Circuit level Benchmarking ! Conclusion

Case study: Arithmetic Circuits Logic Gates (FO4 delay) Arithmetic Cell Library (31, 5) Parallel counter 22% S CG D Control gate Source Source Wallace tree (54 x 54 multiplier) 38% Drain PG (11, 2)-reduction tree (16 x 16 MAC) 45% Polarity gate (29, 3)-compressor 40% Area 16-bit carry-select adder 22% 22.7% 5-bit ripple-carry adder 0 100 200 300 400 500 600 700 800

Case study: Arithmetic Circuits Logic Gates Arithmetic Cell Library 63.8% (31, 5) Parallel counter 61.8% Wallace tree (54 x 54 multiplier) 57.6% (11, 2)-reduction tree (16 x 16 MAC) 66% (29, 3)-compressor Delay 16-bit carry-select adder 71.7% 66% 5-bit ripple-carry adder 0 10 20 30 2.8x improvement

Circuit Level Benchmarking Benchmark Circuits TCAD-based Generate Tiles table model Physical Synopsys Design Delay Synthesis onto Compiler Encouter Library Sea-of-Tiles Characterizer Leakage TECHNOLOGY MAPPING 1.8x improvement

Outline ! Introduction ! Layout Technique for DG-SiNW FET ! Sea-of-Tiles ! Simulation Results ! Conclusion

Conclusion � ! Proposed a novel layout methodology and algorithm for Boolean functions with embedded XOR ! Showed an efficient implementation of Ambipolar circuits with Sea-of-Tiles design methodology # Area optimal tiles Tile G2 and Tile G1h2 ! Circuit Level Benchmarking # Maximum improvement for Arithmetic circuits (2.8x) # Reduction in Leakage power (16x)

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