Jaiseung Bang, Vincent Liao, Arunagiri Venkatesan, David Yang CSEE - PowerPoint PPT Presentation

Jaiseung Bang, Vincent Liao, Arunagiri Venkatesan, David Yang CSEE W4840 Spring 2011 Final Project

The Idea

Downscaling

Silhouette Generation -­‑ ¡ = ¡

Downscaling

High Level Overview Camera VGA Monitor Altera DE2 Board 640x480 NTSC Video VGA via Composite signals ADV7181 Mode Buttons Altera Cyclone II I2C Background FPGA YCbCr Capture Button 7 Segment Displays

Architecture I2C to from mode YCbCr video ADV7181 buttons from ADV7181 to 7 seg displays I2C Config to VGA display Video from background Decoder capture button Background VGA YCbCr data RAM Controller and X/Y coordinates Downscaler Foreground RAM ball downscaled data downscaled data coordinates data and X/Y coordinates and X/Y coordinates of detected silhouette Silhouette Generator SRAM Data Transfer Avalon Bus NIOS CPU

Design Decisions • Block RAM • 27MHz Clock • Game Change

Issues • RAM Issue • Clock Issue

Goalie Mode block green balls

Dodge Mode avoid red balls

Ninja Mode block green balls avoid red balls

Lessons Learned • TD_Reset • 1 Dimensional Arrays • 27Mhz VGA Clock

THANK YOU