DATICS-NESEA ’ 10 Jai Narayan Tripathi -IIT Bombay, INDIA.Rajkumar Nagpal - STMicroelectronics, INDIA.Rakesh Malik - STMicroelectronics, INDIA.
Agenda ● Background ● High Speed Issues : A System Perspective - Signal Integrity - Power Integrity - Bit error rate (BER) – Jitter and Amplitude Noise ● System Level Model -System Level modeling and Simulation. ● Introduction to DOE - Full Factorial Experiments - Fractional Factorial Experiments - Robust Optimization ● Model Used : SI-PI as a Dual ● Statistical Analysis - Quality Parameters and factors - Orthogonal Array or Treatments - Analysis and Optimization ● Final Design ● Results and Conclusion
� Existing Designer flow. ! In normal Design flow System level environment is not considered. ! This leads to multiple iterations for design maturity in real application environment. � Present work ! Proposal for System level simulations in Design flow ! The present work proposes a robust system level design flow taking into consideration effects " Signal Integrity affects. " Power Integrity affects. coming from package, board, test fixtures and measuring equipments etc. ! Sensitivity parameters affecting system performance are defined. ! Finally using an efficient statistical optimization (DOE), sensitive parameters optimization for better yield and manufacturability are derived. ! This analysis has been done using a real design (USB HSLINK) and improvement in design robustness has been demonstrated with eye diagram improvement ! This robust flow will save multiple Silicon iterations.
High Speed Issues ● Reliable transmission at higher speeds is difficult and challenging. ● System complexity is increasing but power supply is reducing in chips. ● System contains chip, package, board, squidd card and cable. ● Integrated analysis of system is difficult. ● How to improve the output response is a challenge at system level.
Design Challenges : USB 2.0 Testchip System ● Used to test USB 2.0 Transceiver chips. ● System contains chip, package, board, squidd card and cable. ● Integrated analysis of system is difficult. ● How to improve the output response is a challenge at system level.
Signal Integrity " Signals come from real world i.e. from outside the chip. " There are various interconnect levels through which the real world signals have to pass. These interconnects are mainly responsible for the SI problems. Signal from chip Final Signal from Board
" Signal distorts with time due to the physical length it has to propagate through. " There are different mechanisms by which signal distorts but the main reasons are " Reflection, Inter Symbol, Interference (ISI). " Insertion Loss, Crosstalk
Power Integrity " Power Integrity deals with the proper supply of power within the system. " To maintain the quality of power supply within the system (i.e. with low fluctuations) is called Power Integrity. A typical power delivery system* *Fig. Reference : Power Integrity : IC, Package and Board Co-Design"; Presentation by Xilinx and Ansoft, Application Workshop for High Performance Design, 14 Nov. 2006 .
" Power Integrity deals with the power delivery paths from a voltage source to active devices (ICs) through boards and packages. " There are three main performance indices of a power delivery systems : 1) Sufficiency [ Source ability to delivery Power] 2) Efficiency [ Minimum loss in PDN] 3) Stability [ Minimum Ripple]
Bit Error Rate/Jitter/Amplitude Noise " BER is calculated by taking the ratio of number of bits misinterpreted to the total number of bits sent or transmitted. " For example in USB 2.0 system, BER of 10 -12 is acceptable, but to achieve a good confidence level, it should be 10 -15 . " BER is mainly due to two reasons : Time Jitter and Amplitude Noise. We ’ ll take both these as our quality parameters for Robust Optimization
" Time Jitter: Jitter is temporal variation in the signal. The rising and falling edges deviate from their ideal position. " Amplitude Noise may cause the misinterpretation at the receiving end. A ‘ 1 ’ can be interpreted as ‘ 0 ’ or vice versa due to noise
Power Delivery Network: " Source Model (Regulator) " Bulk capacitors. " Board Power Plane model. " Decoupling Network. " Package Power planes. " Bond Wires. Signal Integrity Environment. " Bond Wires. " Differential traces at Package/Vias " Differential traces on Characterization/Application board. " Test Fixture board differential traces model. " Termination Environment. " Test equipment probing environment
" “ Quality Engineering ” is a branch of engineering that deals with the yield and the quality of the production. " In the paper, DOE techniques are used for Robust Optimization of USB 2.0 System. " For Orthogonal Experiments, Taguchi Methods are used to optimize or diagnose the system.
Design Of Experiments (DOE) ● Method to efficiently design a system to maintain it ’ s important output parameters within the robustness limits of the functionality of the system. Full Factorial Experiments: It considers all the possible combinations and based on the results, optimization is performed. E.g. in our circuit there will be 3 13 = 1594323 experiments
Fractional Factorials : This method facilitates to perform only certain combinations out of all the possible combinations. The set of experiments can be defined either by an orthogonal array, or by forming a subgroup of the direct product of Abelian groups of orders equal to the number of levels of each factor.
In our case, we are performing 27 certain combinations i.e. experiments, instead of 1594323 experiments (more than one million). These combinations are taken according to Orthogonal Array (L 27 ). Orthogonal Arrays provide best possible information in least no. of simulations.
Stepsfor Robust Optimization
Design Variables (Physical) or Control Factors for DOE 1) Board power plane metal thickness (b1) 2) Board power plane substrate thickness (b2) 3) Board power plane dielectric constant (b3) 4) Board signal trace width (b4) 5) Board signal trace length (b5) 6) Board traces differential pair spacing (b6) 7) Package via diameter (p1) 8) Package signal net width (p2) 9) Package signal net differential gap (p3) 10) Package dielectric constant (p4) 11) Diameter of crossection of wire bonds (w1) 12) Angle of wire bonds (w2) 13) Termination at receiver (t)
Taguchi Arrays & Simulations
Statistical Analysis " From Ordinary Least Square (OLS) methods the sensitivity coefficients for each parameter are following : " These are the vectors containing sensitivity coefficients of b1, b2, # . ,w1,w2, t for Jitter and Eye Amplitude respectively. " [A] is the experimental matrix. " The modeling may not contain some of the uncontrollable factors and their effect on Jitter and eye Amplitude. The effect by them is called ‘ error ’ .
The above values of R2 indicate that some of the parameters are not taken into account for variation. This is mainly due to PLL jitter in die, which is ignored. For all the simulations, the netlist included is USB 2.0 high speed transceiver netlist which considers an ideal clock source. While taking PLL into account for simulation, the time for simulation becomes very long (in days). For such a statistical analysis (which has been used in the paper), which requires a lot of simulations, this is not feasible including PLL into system.
Parameter Normalization 1) Sensitivity Functions: Since all the design parameters are having different units of measurement i.e. m; inch; etc., thus to formulate the Quality Parameters as the function of various design parameters, it is necessary to normalize all the design parameters. To normalize a design parameter x, the process is : After normalization of all the design parameters and finding their sensitivity coefficients, we can find the expression of Quality Parameters as linear function of design parameters. Based on the values from above equations (and given in table IV) the formulation for Jitter and Amplitude noise are :
Best Settings After observing the effect of each parameter, the best settings can be predicted. This can also be done by observing the curves. Thus the best settings are : b5 : -3 p1 : +3 p2 : -3 p3 : -3 w2 : -3 All other parameters will be at initial values.
Results Comparison between initial and final designs
Conclusion There is 20 % improvement in Jitter with 1.6 % improvement in Eye Height. A step by step and systematic method is set for system level parameters improvement.
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