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Invyswell: A HyTM for Haswell RTM Irina Calciu, Justin Gottschlich, - PowerPoint PPT Presentation

Invyswell: A HyTM for Haswell RTM Irina Calciu, Justin Gottschlich, Tatiana Shpeisman, Gilles Pokam, Maurice Herlihy Multicore Performance Scaling u Problem: Locking u Solution: HTM? u IBM BG/Q, zEC12, POWER u Intel Haswell TSX


  1. Invyswell: A HyTM for Haswell RTM Irina Calciu, Justin Gottschlich, Tatiana Shpeisman, Gilles Pokam, Maurice Herlihy

  2. Multicore Performance Scaling u Problem: Locking u Solution: HTM? u IBM BG/Q, zEC12, POWER u Intel Haswell TSX Source: embedded.com 2

  3. Restricted Transactional Memory (RTM) xbegin() Atomic region called transaction xend() Execute optimistically, without any locks Read and Write Sets Abort on memory conflict: programmer defined behavior 3

  4. RTM Fallback: Global Lock if (xbegin() == XBEGIN_STARTED) Execute Transaction xend() else Execute Fallback Path 4

  5. Lock Elision Source: Anand Tech 5

  6. Why Lock Elision Is Not Enough 4.5 ¡ NorecSTM ¡ 4 ¡ NorecHy ¡ 3.5 ¡ 3 ¡ HLE ¡ Speedup ¡ 2.5 ¡ 2 ¡ 1.5 ¡ 1 ¡ 0.5 ¡ 0 ¡ 1 ¡ 2 ¡ 4 ¡ 8* ¡ Threads ¡ Labyrinth

  7. InvalSTM (prior work) u [Gottschlich et al., CGO 2010] u Scalable u Good for large transactions u Conflict detection using bloom filters 7

  8. InvalSTM Software Transaction (prior work) Main body of SW txn On read: SW Add to read Bfilter Txn On write: Add to write Bfilter Add writes to hash table Time If can_commit() Invalidation Invalidation Else restart update memory Commit 8

  9. InvalSTM Invalidation (prior work) Inflight Transactions C o n f l i c t s ? ( u s i n g b l o o m f i l t e r s ) Contention Manager Can I commit? Committing Transaction 9

  10. InvalSTM Invalidation (prior work) Inflight Transactions yes no no Contention Manager T R O B A Committing Transaction 10

  11. InvalSTM Invalidation (prior work) Inflight Transactions Contention Manager Aborted 11

  12. InvalSTM Invalidation (prior work) Inflight Transactions yes no no Contention Manager T I M M O C Committing Transaction 12

  13. InvalSTM Invalidation (prior work) Inflight Transactions E T A D I L A Contention V N I Manager Committed 13

  14. Software Transaction (InvalSTM) SW Txn Time Invalidation Commit 14

  15. Hardware Transaction + Invalidation HW Txn Time ABORT Invalidation Commit 15

  16. Hardware Transaction + Invalidation HW Txn Time COMMIT Commit (Check BF) Already committed, can’t abort Invalidation 16

  17. Software Transaction (Modified InvalSTM) SW Txn Time Commit Invalidation 17

  18. x = 2; y = 1; SW Transaction 1 SW Transaction 2 (commit) (execution) Read x; Time x++; y++; Read y; z = 1/0!!! z = 1/(x - y); (invalidation) ABORT 18

  19. Read Validation SW Transaction 1 SW Transaction 2 (commit) (execution) Check BF ABORT Read x; Time x++; y++; Check BF Read y; z = 1/(x - y); 19

  20. SPECSW (Speculative Software) Begin SW txn, increment sw_cnt Main body of SW txn On read: SW Validate and add to read Bfilter On write: Add to write Bfilter Time Add writes to hash table Acquire commit_lock Validate Commit If can_commit() update memory Else release lock and restart Post- Invalidation Commit Decrement sw_cnt, release lock 20

  21. BFHW (Bloom Filters Hardware) xbegin() Main body of HW txn. HW On Read: add to read Bfilter On Write: add to write Bfilter Time if (commit_lock) if (BF conflict()) xabort() Commit xend() Post- Invalidation Commit 21

  22. x = 2; y = 1; HW Transaction 1 SW Transaction 2 (commit) (execution) Read x; Time x++; y++; Read y; ABORT z = 1/0!!! z = 1/(x - y); (invalidation) ABORT 22

  23. Read Validation HW Transaction 1 SW Transaction 2 (commit) (execution) Check BF Read x; Time x++; y++; Check BF Read y; z = 1/(x - y); 23

  24. BFHW xbegin() Main body of HW txn. HW On Read: add to read Bfilter Time On Write: add to write Bfilter if (commit_lock) if (BF_conflict()) xabort() Commit ++hw_post_commit; xend() Post- Invalidation Commit --hw_post_commit (fetch_and_sub) 24

  25. Read Validation HW Transaction 1 SW Transaction 2 (commit) (execution) Wait for hw_post_commit == 0 Read x; Time x++; y++; Wait for hw_post_commit == 0 Read y; z = 1/(x - y); 25

  26. BFHW SPECSW Expensive! SW On Read: add to read Bfilter HW On Write: add to write Bfilter Time Commit Commit Invalidation Post- Expensive! Commit Post- Commit 26

  27. LITEHW (Light Hardware) xbegin() HW Main body of HW txn. Time if (sw_cnt) xabort(); Commit else xend() 27

  28. Ensuring Progress Inflight Transactions Contention Manager Committing SW Transaction 28

  29. Ensuring Progress Inflight Transactions Contention Manager Committing Committing HW SW Transaction Transaction 29

  30. Does not abort – Guarantees Progress IRREVOCSW (Irrevocable Software) Acquire commit lock, increment sw_cnt Main body of SW txn. SW Time On Read: add to read Bfilter Expensive! On Write: add to write Bfilter Use direct updates Do nothing Commit (Changes are already committed) Post- Expensive! Invalidation Commit Decrement sw_cnt, release lock 30

  31. SGLSW (Single-Global-Lock Software) Acquire commit lock, increment sw_cnt ++commit_sequence Main body of SW txn. SW Use direct updates Time Do nothing Commit (Changes are already committed) Post- ++commit_sequence Commit Decrement sw_cnt, release lock 31

  32. Invyswell State Diagram Start no yes SW txns running? retry retry small txns with unsupported LiteHW BFHW HTM instructions retry threshold retry threshold exceeded exceeded SglSW large txns with unsupported HTM instructions / overflow retry retry threshold exceeded IrrevocSW SpecSW conflict

  33. Invyswell State Diagram Fail-fast? Start yes no no yes SW txns running? retry retry small txns with unsupported LiteHW BFHW HTM instructions / fail-fast retry threshold retry threshold exceeded exceeded SglSW large txns with unsupported HTM instructions / overflow retry SpecSW

  34. Concurrent Execution Matrix

  35. Speedup

  36. Speedup

  37. Speedup

  38. Transaction Types – 1 Thread % transactions benchmarks

  39. Transaction Types – 8 Threads % transactions benchmarks

  40. Conclusions u HLE and RTM w/ SGL fallback are not enough u Invyswell is 35% faster than NOrec, 18% faster than Hybrid NOrec and 25% faster than HLE across all STAMP benchmarks

  41. Thank you! u http://cs.brown.edu/~irina u irina@cs.brown.edu

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