Introduction to Xilinx System Generator Part I Evan Everett and - PowerPoint PPT Presentation

Introduction to Xilinx System Generator Part I Evan Everett and Michael Wu ELEC 433 - Spring 2013

Outline • Introduction to FPGAs and Xilinx System Generator • System Generator basics • Fixed point binary numbers • Fixed point arithmetic • Sample times • Tips for building models

FPGA Basics: Architecture

FPGA Basics: Architecture Slice Switch Matrix Slice Slice Slice Configurable Logic Blocks I/O Buffers Multiplier Digital Clock Block RAM Manager

FPGA Basics: Architecture Configurable Logic Block Slice Slice MUX Register LUT MUX Slice Switch Matrix Register LUT Slice Misc Logic Lookup Tables (LUTs) Slice implement any 4-input logic function

FPGA Basics: Glossary • LUT: lookup table • MUX: multiplexer • MULT: embedded multiplier • Slice: atomic logic block containing 4 LUTs and 8 flip flops • DSP Slice: slice containing an adder, accumulator and multiplier • CLB: configurable logic block • BRAM: block random access memory

FPGA Basics: Resources Example Resources for Xilinx Virtex family FPGAs 18 Kb Device Slices DCMs Mults I/O BRAMs Virtex-2 Pro 23,316 8 232 232 852 XC2VP50 Virtex-4 42,176 12 160 376 768 XC4VFX100 Virtex-6 37,680 12 768 832 720 LX240T Virtex-7 63,400 12 2,160 1,760 600 XC7VX415T

FPGA Basics: Resources Example Resources for Xilinx Virtex family FPGAs 18 Kb Device Slices DCMs Mults I/O BRAMs Virtex-2 Pro 23,316 8 232 232 852 XC2VP50 Virtex-4 42,176 12 160 376 768 v3 uses this chip XC4VFX100 Virtex-6 37,680 12 768 832 720 LX240T Virtex-7 63,400 12 2,160 1,760 600 XC7VX415T

How do we target these resources? • Hardware description languages (HDL) like Verilog/VHDL allow designers to specify at a higher level than logic gates • We will use an even higher level tool called System Generator • Graphical programming environment within Matlab’s Simulink

System Generator Basics • System Generator provides two key tools • Blocks for building your model • Hardware generator: model → HDL • Simulink provides a test environment for your design • Generate test vectors with MATLAB or Simulink blocks • Visualize and analyze output of design • Leverage MATLAB expressions within design • Simulation and hardware will match “bit true” and “cycle true ”

System Generator MATLAB fir(10,0.2) sin(0:1024./pi) Simulink SysGen Xilinx Blocks Bit True Generate VHDL

System Generator Example Simulink Blocks Simulink Blocks Xilinx Blocks • Simulink blocks are your signal sources and sinks • Xilinx blocks are your to-be-synthesized FPGA design

System Generator Example System Generator Blocks • These will be realized in hardware

System Generator Example System Generator Token • Configures simulation & hardware parameters • Relates sample period to hardware clock • Used to synthesize model • Sets target FPGA device for model

System Generator Example Simulink Blocks • Must be outside System Generator gateways • Operate on floating point values • Good for data sources & analysis • Source: continuous-time floating point constant • Sink: signal vs. time scope

System Generator Example Gateway Blocks • Convert between floating and fixed point values • Top-level ports in HDL model • Must set precision & sample rate in Gateway In

System Generator Basics • Every model needs a System Generator token • Models start and end with Gateway blocks System Generator • : double to fixed point conversion • : fixed point to double conversion • Any Simulink blocks can be used outside gateways • Good for data sources and output analysis • Only Xilinx blocks can be used inside gateways • Synthesis treats gateways as top-level ports