Introduction - Agenda What is Physical Synthesis? What is PC? - PowerPoint PPT Presentation

Introduction - Agenda What is Physical Synthesis? What is PC?

Design Sizes are Increasing Rapidly � Continuous increase in the Performance (MHz) Gates (millions) number of available gates 600 18 � New silicon technologies present challenges to Performance 15 designers and tools 450 Gates 12 � Designers continue to create larger, faster designs that 9 300 are stressing current design 6 methodologies 150 3 1995 1998 2001 2004 0.5u 0.25u 0.13u 0.09u

Deep Sub-Micron Design Challenge For the same length of wire, interconnect delays are much longer for two reasons: • Wires are closer together • Wires are narrower Delay RC Delay 3.0 As the gate delay goes down, the path 2.0 is swamped by the net delays 1.0 Gate Delay 0.0 Microns 1.00 0.75 0.50 0.25 0.13

Designs Are Not Getting Done on Time Design Looks Okay, But,... Synthesis Number of Timing Errors with Wire Load Models …after P&R, the timing is bad Netlist Netlist SDF SDF After 1st After 2nd After 3rd Place and Route Synthesis Synthesis Reoptimization (WLM) (CWLM) (SDF) Poor estimates lead to After 1st After 3rd After 2nd timing closure problems P&R P&R P&R Synthesis result P&R result

WLM � Worst-Case Interconnect Delay 0.6 Process Net delay = ~1ns ~10% of clock period for 100MHz design 2-3x gate delay 0.25 Process Net delay = ~4.5ns ~40% of clock period for 100MHz design 20x gate delay 0.18 Process (Cupper) Net delay = ~6.0ns ~60% of clock period for 100MHz design Logical Effort Can’t tell the Story 40x gate delay

Wireload vs. physical synthesis 1. Front-end timing (wireload based) is becoming unreliable 2. Placement can change timing dramatically: � After placement, it is obvious that nets with the same fanout will not have the same interconnect delay Physical View Logical View

Placement is The Key! � Logic Design is optimized for the current Floorplan Timing Accuracy (% Error) With Physical Synthesis, designer “sees” more � accurate physical effects � Placement is an Important key WLM “Design closure” – timing/area/congestion/power/… � ±100 % � Drastically reduces iteration between logic synthesis and P&R Netlist handoff based on WLM timing can still cause � iterations between logic synthesis and physical synthesis Interconnect Models Placement Coarse Route Track Assignment Detail Route Design 0 % Physical Synthesis Post Layout Phase Synthesis

Expectations from Physical Synthesis Results RTL source ( .v .vhd ) Floorplan Physical Compiler Placed Gates Output design is a legal fully placed floorplan that is router ready: � Design can be routed with no modifications � Design is fully optimized for timing and routing congestion

Expectations for One Pass Timing Closure I/O Pad Driver � No WLM used � Placement Based Delay � Individual Net Load RAM estimated � Macro Cell Placement honored Receiving Gates � Layout Data considered � Consistent Timing Model

Introduction- Agenda What is Physical Synthesis? What is PC?

What is Physical Compiler ? � Placement knowledgeable synthesis and optimization tool: Unifies synthesis and placement � Concurrently produces an optimized gate-level netlist AND � physical cell placement from either � RTL description � Existing gate-level netlist Net delays are based on actual placement of cells, not wire load � models Resulting netlist is “router ready” � � Built on top of logic synthesis infrastructure: Common database, Tcl interface, constraints, timing engine, � synthesis libraries

What is Physical Compiler II ? Block-Level Designs RTL or GATES Logical library F n l r e g e x i l P s i p e l Placement Physical Synthesis a m D c o e library C Physical Compiler Constraints Global Router Congestion Analysis & Removal Physical Constraints DesignTime Timing Calculation Netlist & Placement

Familiar Synthesis Process Synthesis Data (DC) Gate-Level Netlist Tcl script .db / .ddc Logical Library Logical Constraints Physical Design Compiler Compiler (P)DEF, .db .ddc, mw . pdb / mw Physical Constraints Physical Library (Floorplan) Physical Data Netlist & Placement

Physical Compiler - Timing engine Block-Level Designs RTL or GATES Logical library F n l r e g e x i l P s i p e l Placement Physical Synthesis a m D c o e library C Physical Compiler Constraints Global Router Congestion Analysis & Removal Physical Constraints DesignTime Timing Calculation Netlist & Placement

Timing Calculations � Calculations use pin-to-pin “intelligent” Steiner Routing � Each net is calculated individually � Net Modeling is Elmore Model � No wire load models are used Steiner Route Driver Pin-to-pin timing With On-rout flow ( physopt –on_route in PCE) Astro route is considered

Physical Compiler Placement engine Block-Level Designs RTL or GATES Logical library F n l r e g e x i l P s i p e l Placement Physical Synthesis a m D c o e library C Physical Compiler Constraints Global Router Congestion Analysis & Removal Physical Constraints DesignTime Timing Calculation Netlist & Placement

Details of FlexPlace � Linear Wire Length Reduction: � Reduces total Manhattan wire length � 10-15% wire length reduction compared to others � Lowers the burden on the routing resources � Global Optimization - No Partitioning! � Optimized placement without partitioning � Avoids artificially partitioned regions and placement constraints � Flexible placement for continuous adjustments � Direct Quality Measures: � Measures linear versus quadratic wire length for improvement � Timing measure incorporated in its cost/objective function

Physical Compiler Block-Level Designs RTL or GATES Logical library F n l r e g e x i l P s i p e l Placement Physical Synthesis a m D c o e library C Physical Compiler Constraints Global Router Congestion Analysis & Removal Physical Constraints DesignTime Timing Calculation Netlist & Placement

Physical Compiler Flow Load design data Load design data Place & optimize Place & optimize Test insertion Test insertion Power optimization Power optimization Incremental No Incremental Timing & congestion Timing & congestion optimization optimization ok? ok? Yes Placed design

Physical Compiler Placement+Optimization IP Gate-Level Netlist Floorplan Physical Optimization IP Placed & Optimized Design

Physical Compiler Work Flow Logical Data Physical Data Physical Optimization Analysis Output

Logical Data Logical Data Logical Libraries Physical Data .db Gate-Level Physical Netlist(s) Optimization Analysis create_clock –period 10 ... link set_input_delay –max 1.2 ... set_output_delay –max 2.5 ... Output set_driving_cell ... ...... Logical (Timing) Constraints check_timing

Reading the Gate-Level Netlist � Physical Compiler reads all netlist formats supported by Design Compiler read_milkyway read_verilog read_vhdl read_ddc … � You can read one or many files read_verilog –netlist file1.v file2.v … gate-level netlist

Logical Libraries � Provide timing and functionality information for all standard cells (and, or, flipflop, …) � Provide timing information for hard macros (ROM, RAM, …) � Define drive/load design rules: � Max/Min fanout Logical Libraries � Max/Min capacitance .db � Max/Min transition � Specified as follows: set link_library "* gates.db io.db mem.db" Search all designs in memory

Where does Physical Compiler find files? � By default, you must specify the complete unix-path for all files � You may specify where to look for files: lappend search_path ./design_data ../libs � The above paths will be used by Physical Compiler for reading or accessing files

Resolving References � Gate-level netlist contains references to standard cells and macros, which are stored in the logical libraries, as well as other logic blocks � The command link will ensure that all references can be resolved nand nor gates.db inv ff * pci_core ip.db risc_core Gate-Level link Netlist(s) sdram_if mem.db

Timing Constraints � Timing Constraints are required to communicate the design’s timing intentions to Physical Compiler � They should be the same used for synthesis with Design Compiler (preferably SDC compatible) source timing_constraints.sdc create_clock –period 10 [get_ports clk] set_input_delay 4 –clock clk \ [get_ports sd_DQ[*]] set_output_delay 5 –clock clk [get_ports sd_LD] set_load 0.2 [get_ports pdevsel_n] set_driving_cell –lib_cell buf5 \ [get_ports pdevsel_n] ...

Timing Check check_timing � Before proceeding, you need to ensure that the design is completely constrained � Physical Compiler will not optimize paths that are not constrained for timing ! � No checking for missing external loads or drive characteristics will be performed! Completeness does not imply correctness!