Intel P6 Intel P6 15-213 Internal Designation for Successor to - PowerPoint PPT Presentation

Intel P6 Intel P6 15-213 Internal Designation for Successor to Pentium Internal Designation for Successor to Pentium “The course that gives CMU its Zip!” n Which had internal designation P5 Fundamentally Different from Pentium Fundamentally Different from Pentium P6/Linux Memory System P6/Linux Memory System n Out-of-order, superscalar operation Oct. 31, 2002 Oct. 31, 2002 n Designed to handle server applications l Requires high performance memory system Resulting Processors Resulting Processors Topics Topics n PentiumPro (1996) n P6 address translation n Pentium II (1997) n Linux memory management l Incorporated MMX instructions n Linux page fault handling » special instructions for parallel processing n memory mapping l L2 cache on same chip n Pentium III (1999) l Incorporated Streaming SIMD Extensions » More instructions for parallel processing 15-213, F’02 – 2 – class20.ppt 32 bit address space 32 bit address space P6 Memory System P6 Memory System Review of Abbreviations Review of Abbreviations 4 KB page size 4 KB page size L1, L2, and L1, L2, and TLBs TLBs DRAM n 4-way set Symbols: Symbols: associative n Components of the virtual address (VA) external inst TLB inst TLB system bus l TLBI: TLB index (e.g. PCI) n 32 entries l TLBT: TLB tag n 8 sets L2 l VPO: virtual page offset data TLB cache data TLB l VPN: virtual page number n 64 entries cache bus n Components of the physical address (PA) n 16 sets inst l PPO: physical page offset (same as VPO) bus interface unit L1 i-cache and d-cache L1 i-cache and d-cache TLB l PPN: physical page number n 16 KB data l CO: byte offset within cache line n 32 B line size TLB l CI: cache index instruction L1 n 128 sets fetch unit i-cache l CT: cache tag L1 L2 cache L2 cache d-cache n unified processor package n 128 KB -- 2 MB – 3 – 15-213, F’02 – 4 – 15-213, F’02

Overview of P6 Address Translation Overview of P6 Address Translation P6 2-level Page Table Structure P6 2-level Page Table Structure 32 CPU Up to Page directory Page directory result L2 and DRAM 1024 n 1024 4-byte page directory page 20 12 virtual address (VA) entries (PDEs) that point to page tables L1 VPN VPO L1 tables miss 1024 hit 16 4 n one page directory per process. PTEs TLBT TLBI page n page directory must be in ... L1 (128 sets, 4 lines/set) directory TLB memory when its process is TLB 1024 1024 hit running ... ... miss PDEs PTEs n always pointed to by PDBR ... TLB (16 sets, 10 10 Page tables: Page tables: 4 entries/set) VPN1 VPN2 1024 20 7 5 20 12 n 1024 4-byte page table entries PTEs CT CI CO PPN PPO (PTEs) that point to pages. physical PDE PTE n page tables can be paged in and address (PA) out. Page tables PDBR 15-213, F’02 15-213, F’02 – 5 – – 6 – P6 Page Directory Entry (PDE) P6 Page Table Entry (PTE) P6 Page Directory Entry (PDE) P6 Page Table Entry (PTE) 31 12 11 9 8 7 6 5 4 3 2 1 0 31 12 11 9 8 7 6 5 4 3 2 1 0 Page table physical base addr Avail G PS A CD WT U/S R/W P=1 Page physical base address Avail G 0 D A CD WT U/S R/W P=1 Page base address: 20 most significant bits of physical page Page table physical base address: 20 most significant bits of physical page table address (forces page tables to be 4KB aligned) address (forces pages to be 4 KB aligned) Avail: These bits available for system programmers Avail: available for system programmers G: global page (don’t evict from TLB on task switch) G: global page (don’t evict from TLB on task switch) PS: page size 4K (0) or 4M (1) D: dirty (set by MMU on writes) A: accessed (set by MMU on reads and writes, cleared by software) A: accessed (set by MMU on reads and writes) CD: cache disabled (1) or enabled (0) CD: cache disabled or enabled WT: write-through or write-back cache policy for this page WT: write-through or write-back cache policy for this page table U/S: user or supervisor mode access U/S: user/supervisor R/W: read-only or read-write access R/W: read/write P: page table is present in memory (1) or not (0) P: page is present in physical memory (1) or not (0) 31 1 0 31 1 0 Available for OS (page table location in secondary storage) P=0 Available for OS (page location in secondary storage) P=0 – 7 – 15-213, F’02 – 8 – 15-213, F’02

Representation of Virtual Address Representation of Virtual Address How P6 Page Tables Map Virtual How P6 Page Tables Map Virtual Space Space • Addresses to Physical Ones Addresses to Physical Ones P=1, M=1 Page 15 • P=0, M=0 PT 3 Page 14 • P=1, M=1 10 10 12 • Page 13 P=0, M=1 Virtual address VPN1 VPN2 VPO Page 12 Page Directory • P=1, M=1 • • word offset into word offset into word offset into Page 11 P=1, M=1 P=0, M=0 PT 2 • • page directory page table physical and virtual P=1, M=1 P=1, M=1 Page 10 • • page P=0, M=0 P=0, M=1 Page 9 • P=0, M=1 • page directory page table P=0, M=1 Page 8 PT 0 • P=0, M=1 Page 7 • P=0, M=0 • Page 6 P=0, M=0 physical Page 5 PTE Simplified Example Simplified Example Mem Addr address Page 4 PDE of page base n 16 page virtual address space Page 3 Disk Addr PDBR (if P=1) physical address Page 2 physical address In Mem Flags Flags of page table base Page 1 of page directory (if P=1) On Disk n P: Is entry in physical memory? Page 0 20 12 n M: Has this part of VA space Unmapped Physical address PPN PPO been mapped? 15-213, F’02 15-213, F’02 – 9 – – 10 – P6 TLB Translation P6 TLB Translation P6 TLB P6 TLB 32 CPU TLB entry (not all documented, so this is speculative): TLB entry (not all documented, so this is speculative): result L2 andDRAM 20 12 32 16 1 1 virtual address (VA) VPN VPO L1 PDE/PTE Tag PD V L1 miss hit 16 4 n V: indicates a valid (1) or invalid (0) TLB entry TLBT TLBI n PD: is this entry a PDE (1) or a PTE (0)? L1 (128 sets, 4 lines/set) TLB n tag: disambiguates entries cached in the same set TLB hit ... ... miss n PDE/PTE: page directory or page table entry l Structure of the data TLB: l Structure of the data TLB: TLB (16 sets, 10 10 VPN1 VPN2 4 entries/set) n 16 sets, 4 entries/set 20 12 20 7 5 PPN PPO CT CI CO entry entry entry entry set 0 entry entry entry entry set 1 physical PDE PTE entry entry entry entry set 2 address (PA) ... entry entry entry entry set 15 Page tables PDBR – 11 – 15-213, F’02 – 12 – 15-213, F’02

P6 page table P6 page table Translating with the P6 TLB Translating with the P6 TLB translation translation 32 CPU 1. Partition VPN into 1. Partition VPN into result L2 andDRAM CPU TLBT and TLBI. TLBT and TLBI. 20 12 virtual address (VA) L1 VPN VPO virtual address 2. Is the PTE for VPN 2. Is the PTE for VPN L1 20 12 miss cached in set TLBI? cached in set TLBI? hit VPN VPO 16 4 TLBT TLBI n 3. Yes: then 16 4 1 TLBT TLBI 2 build physical L1 (128 sets, 4 lines/set) TLB TLB address. hit TLB ... ... miss TLB hit PDE PTE 3 4. No No: then read PTE (and : then read PTE (and 4. ... miss PDE if not cached) 20 12 PDE if not cached) TLB (16 sets, 10 10 PPN PPO from memory and from memory and 4 entries/set) VPN1 VPN2 physical 20 7 5 build physical 20 12 build physical address CT CI CO page table translation PPN PPO address. address. 4 physical PDE PTE address (PA) Page tables PDBR 15-213, F’02 15-213, F’02 – 13 – – 14 – Translating with the P6 Page Tables Translating with the P6 Page Tables Translating with the P6 Page Tables Translating with the P6 Page Tables (case 1/1) (case 1/0) (case 1/1) (case 1/0) Case 1/0: page table Case 1/0: page table present but page present but page 20 12 missing. missing. Case 1/1: page VPN VPO Case 1/1: page 20 12 VPN VPO table and page table and page MMU Action: MMU Action: present. present. VPN1 VPN2 20 12 n page fault exception VPN1 VPN2 PPN PPO MMU Action: MMU Action: n handler receives the following args: n MMU builds Mem Mem PDE p=1 PTE p=0 l VA that caused physical PDE p=1 PTE p=1 data fault address and PDBR Page Page l fault caused by fetches data PDBR directory Data table Page Page non-present page word. page directory table or page-level l OS action l OS action protection violation data Disk Disk l read/write n none l user/supervisor Data page – 15 – 15-213, F’02 – 16 – 15-213, F’02