Integrated Retiming and Simultaneous Vdd/Vth Scaling for Total Power Minimization Mongkol Ekpanyapong Advisor: Prof. Sung Kyu Lim School of Electrical and Computer Engineering Georgia Institute of Technology
Outline � Introduction and Motivation � Related Work � Methodology � Experimental Results � Conclusions 2 May, 2006
Introduction � Both static and dynamic power are the important issue in deep submicron design � Performance is important issue � The objective of this work is to minimize total power consumption while maintain the target clock period 3 May, 2006
Retiming Algorithm � Linear Programming � Can easily be modified to handle any linear objective � Bellman-Ford Algorithm � Can handle large circuits 4 May, 2006
Power Minimization � Minimize total number of Flip-flop to reduce flip-flop power � Using dual Vdd and Vth to minimize static and dynamic power 5 May, 2006
Outline � Introduction and Motivation � Related Work � Methodology � Experimental Results � Conclusions 6 May, 2006
Retiming and Voltage Scaling � C . E . Leiserson and J . B . Saxe , “Retiming synchronous circuitry , ” Algorithmica 1991 � K . Usami and M . Horowitz , “Clustered Voltage Scaling Technique for Low - Power Design“ , ISLPED 1995 � N . Chabini and W . Wolf , “Reducing Dynamic Power Consumption in Synchronous Sequential Digital Designs Using Retiming and Supply Voltage Scaling , ” TVLSI 2004 7 May, 2006
Outline � Introduction and Motivation � Related Work � Methodology � Experimental Results � Conclusions 8 May, 2006
Power Minimization with Retiming Circuit Description RETIMING Fixed Target Clock Period Voltage Scaling (LP) 9 May, 2006
Retiming Formulation Objective: Minimize the number of flip-flops (FF.) Constraints: � Num. FF. has to be satisfied r(u) ≤ w(e u,v ) + r(v) � Num. FF. on critical paths has to be greater than zero w r (e) w(e) 0 0 1 0 1 0 0 0 SET 1 2 S Q 3 R Q CLR r(v) 0 0 0 r(v) 0 1 0 V is the set of gates and E is the set of edges. v ∈ V and e ∈ E r(v) is the number of FF. moved from fanout of node v to fanin of node v w(e u,v ) is the FF. count on edge u,v, D(u,v) is the maximum delay on path u,v 10 W(u,v) is minimum number of FF. on path u,v May, 2006
Retiming Formulation Objective: Minimize the number of flip-flops (FF.) Constraints: � Num. FF. has to be satisfied r(u) ≤ w(e u,v ) + r(v) � Num. FF. on critical paths has to be greater than zero 0 4 SET S Q R Q CLR SET 1 2 S Q 3 R Q CLR r(v) 0 0 0 r(v) 0 1 0 V is the set of gates and E is the set of edges. v ∈ V and e ∈ E r(v) is the number of FF. moved from fanout of node v to fanin of node v w(e u,v ) is the FF. count on edge u,v, D(u,v) is the maximum delay on path u,v 11 W(u,v) is minimum number of FF. on path u,v May, 2006
Retiming Formulation Objective: Minimize the number of flip-flops (FF.) Constraints: � Num. FF. has to be satisfied r(u) ≤ w(e u,v ) + r(v) � Num. FF. on critical paths has to be greater than zero Only these 2 FF. can move out of u SET SET u S Q v S Q R Q R Q CLR CLR V is the set of gates and E is the set of edges. v ∈ V and e ∈ E r(v) is the number of FF. moved from fanout of node v to fanin of node v w(e u,v ) is the FF. count on edge u,v, D(u,v) is the maximum delay on path u,v 12 W(u,v) is minimum number of FF. on path u,v May, 2006
Retiming Formulation Objective: Minimize the number of flip-flops (FF.) Constraints: � Num. FF. has to be satisfied r(u) ≤ w(e u,v ) + r(v) � Num. FF. on critical paths has to be greater than zero Cycle Time (L) =2 r(1)-r(3) ≤ 0 r(1) ≤ r(3) SET 1 2 S Q 3 D(1,2) = 2 W(1,2) = 0 R Q CLR D(1,3) = 3 W(1,3) = 1 D(2,3) = 2 W(2,3) = 1 V is the set of gates and E is the set of edges. v ∈ V and e ∈ E r(v) is the number of FF. moved from fanout of node v to fanin of node v w(e u,v ) is the FF. count on edge u,v, D(u,v) is the maximum delay on path u,v 13 W(u,v) is minimum number of FF. on path u,v May, 2006
Retiming Formulation Objective: Minimize the number of flip-flops (FF.) Constraints: � Num. FF. has to be satisfied r(u) ≤ w(e u,v ) + r(v) � Num. FF. on critical paths has to be greater than zero Cycle Time (L) =2 r(1)-r(3) ≤ 0 r(1) ≤ r(3) SET 1 2 S Q 3 D(1,2) = 2 W(1,2) = 0 R Q CLR D(1,3) = 3 W(1,3) = 1 D(2,3) = 2 W(2,3) = 1 V is the set of gates and E is the set of edges. v ∈ V and e ∈ E r(v) is the number of FF. moved from fanout of node v to fanin of node v w(e u,v ) is the FF. count on edge u,v, D(u,v) is the maximum delay on path u,v 14 W(u,v) is minimum number of FF. on path u,v May, 2006
Non-critical Gates for Power Minimization SET SET S S Q Q R R Q Q CLR CLR Non-critical gates: What should we do? We can use the voltage scaling for non-critical gates after retiming to minimize total power consumption 15 May, 2006
May, 2006 16 Low-to-High V dd Conversion � Level Converter (LC) requirement LC
Voltage Scaling Formulation Objective: Minimize gate power + LC power Constraints: Each gate has to be assigned to only one voltage state Arrival time + gate delay of each node ≤ target clock period Level converter inserted if low V dd node drives high V dd node 17 May, 2006
Voltage Scaling Formulation v V dd High V th Low (x v,4 =1) v V dd High V th High (x v,3 =1) v v V dd Low V th Low (x v,2 =1) V dd Low V th High (x v,1 =1) v 18 May, 2006
May, 2006 19 s(v) = 1 v Voltage Scaling Formulation d(u) = 1 s(u) = 0 u
May, 2006 20 s(v) = 2 v Voltage Scaling Formulation d(w) = 1 d(u) = 1 s(w) = 1 s(u) = 0 w u
Voltage Scaling Formulation Cycle time (L) = 2 s(v) = 1 s(u) = 0 d(u) = 1 d(v) = 1 u v s(u) + d(u) ≤ 2 s(v) + d(v) ≤ 2 21 May, 2006
May, 2006 22 V H m(e) = 1 LC Voltage Scaling Formulation V L
Convert from ILP to LP 0.5 0.6 0.3 0.6 0.3 0 0.5 0.3 0.0 0.4 0.8 0.8 1 0 0 0.0 0.0 m(e) x u,1 =1 x u,2 =0 V L 0 = low Vdd x u,2 = x(u) x u,1 =0 x u,2 =1 1 = high Vdd V H Assume only two states for illustration purpose 23 May, 2006
Gradient Search Algorithm for LC Relaxation Solve LP m th = 0.5 Compute new m th 0.5 0.6 1 0 0.3 1 0.6 0 0 0.3 0.5 1 0.3 0.0 0.4 0.8 0.8 Solve LP by setting m(e) = 0 if m(e) < mth 1 0 Otherwise m(e) = 1 0 0.0 0.0 Relax LP solution While |Gain| > Threshold Return 24 May, 2006
Gradient Search Algorithm for LC Relaxation Solve LP m th = 0.5 Compute new m th 0.5 0.3 1 0 1 0 0 1 0.3 0.0 0.3 0.4 0.8 0.7 0.7 0.8 Solve LP by setting m(e) = 0 if m(e) < mth 1 0 Otherwise m(e) = 1 0 0.0 0.0 Relax LP solution Voltage Assignment Relaxation While |Gain| > Threshold Return 25 May, 2006
Voltage Assignment Four possible voltage assignment: � High V dd , low V th node Fastest gate, high dynamic power, high leakage power � High V dd , high V th node High dynamic power, low leakage power � Low V dd , low V th node Low dynamic power, high leakage power � Low V dd , high V th node Slowest gate, low dynamic power, low leakage power 26 May, 2006
Possible Supply Voltage Assignment Feasible Solution Infeasible Solution V H V H V H V H LC V L V H V L V H LC V H V L V H V L LC V L V L V L V L LC 27 May, 2006
May, 2006 28 LP Relaxation for Voltage State Assignment high Vdd low Vdd v V H V L LC u
May, 2006 29 LP Relaxation for Voltage State Assignment high Vdd low Vdd 0.7 v V H V L u
May, 2006 30 LP Relaxation for Voltage State Assignment high Vdd low Vdd v V H V L LC u
LP Relaxation for Voltage State Assignment Assigned V dd High to V Slk = 2.2 v v v Dly = 1 Dly = 2.1 high V dd low V th high V dd high V th 31 May, 2006
LP Relaxation for Voltage State Assignment Assigned V dd High to V Slk = 1.5 v v v Dly = 1 Dly = 2.1 high V dd low V th high V dd high V th 32 May, 2006
LP Relaxation for Voltage State Assignment 0.3 0 1 0 1 0 0 0 1 0.3 0.0 0.3 0.7 0.7 0 1 0 0.0 0.0 Assume only two states V L V H 33 May, 2006
Gradient Search Algorithm for LC Relaxation Compute for next m th Solve LP m th = 0.6 m th = 0.5 Compute new m th 0.5 0.3 0.6 1 0.3 0 0.6 1 0 0 0.3 0.5 1 0.3 0.8 0.7 0.0 0.3 0.4 0.7 0.8 Solve LP by setting m(e) = 0 if m(e) < mth 1 0 Otherwise m(e) = 1 0 0.0 0.0 Relax LP solution While |Gain| > Threshold Return 34 May, 2006
May, 2006 35 Post Refinement
Outline � Introduction and Motivation � Related Work � Methodology � Experimental Results � Conclusions 36 May, 2006
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