ATLAS MDT ASD_V4 Design May 29 th , 2017 Federica Resta Marcello - PowerPoint PPT Presentation

ATLAS MDT ASD_V4 Design May 29 th , 2017 Federica Resta Marcello De Matteis andrea.baschirotto@sparklingic.com

ASDv4 Outline  Channel Block Scheme   Charge Sensitive Preamplifier  Differential Amplifiers  Wilkinson ADC  Measurements Summary  Conclusion ATLAS MDT ASD DESIGN REVIEW 5/26/17 2 of 26

ASDv4 Channel Block Scheme Fig. 1 – Channel Block Scheme. ATLAS MDT ASD DESIGN REVIEW 5/26/17 3 of 26

ASDv4 Channel Critical Design Points (1/2)  CMOS Technological Node o 130nm o 3.3V Supply Voltage o V TH Reduction  0.45V vs 0.75V o Sligth Reduction of intrinsic MOS gain o Smaller Signal o Substrate influenced by rail-to-rail digital signals o Smaller Area  Detector Parasitic Capacitance o 60pF Required a CAREFUL CSPreamp Design ATLAS MDT ASD DESIGN REVIEW 5/26/17 4 of 26

ASDv4 Channel Critical Design Points (1/2)  CSPreamp o INPUT and KEY BLOCK  Charge to Voltage Conversion o Essential Matlab Model for performance optimization  Noise  Sensitivity  Peaking Time Delay  Parasitic Capacitance at CSPremp Output o To guarantee a good conversion speed ATLAS MDT ASD DESIGN REVIEW 5/26/17 5 of 26

ASDv4 Outline  Channel Block Scheme  Charge Sensitive Preamplifier   Differential Amplifiers  Wilkinson ADC  Measurements Summary  Conclusion ATLAS MDT ASD DESIGN REVIEW 5/26/17 6 of 26

ASDv4 Charge Sensitive Preamplifier  Pseudo-Differential Structure o 2 identical Charge Sensitive Amplifiers  CSPreamp  CSPreamp Dummy  Feedback Components: o C F o R F =R F1 +R F2 ATLAS MDT ASD DESIGN REVIEW 5/26/17 7 of 26

ASDv4 Charge Sensitive Preamplifier ��� �� ��� � ����� � � � ∙��� �� �� ��� �� ������� ��∙���� �� � �� � ��� �  With o Detector Capacitance (C D ) o Feedback Capacitance (C F ) o Feedback Resistor (R F =R F1 +R F2 ) o Load Resistor (R L ) o DC Loop Gain (g m1 ∙R L ≈400) o C D /C F ≈88 ATLAS MDT ASD DESIGN REVIEW 5/26/17 8 of 26

ASDv4 Charge Sensitive Preamplifier ��� �� ��� � ����� � � � ∙��� �� �� ��� �� ������� ��∙���� �� � �� � ��� �  Choosing o R L =R F o g m1 >>1/R F  High Frequency Zero (≈5GHz)  CSPreamp Transfer Function can be approximated to: � � ����� � � � ∙����∙ �� ������� ��∙���� �� � ��� � �� ∙ ATLAS MDT ASD DESIGN REVIEW 5/26/17 9 of 26

ASDv4 CSPreamp Dominant Pole  Ideal Case: o Open Loop Amplifier has  Infinitive gain  Infinitive bandwidth o Ideal Dominant Pole Constant  � � � o Ideal Sensitivity  ���,����� � �  Finite DC Gain (g m1 ∙R L ≈400) � � � o Dominant Pole Constant  � �� � � � � � � � o Sensitivity  ��� ���,����� ���,����� ���∙ �� � �� ∙ ���∙�� ATLAS MDT ASD DESIGN REVIEW 5/26/17 10 of 26

ASDv4 CSPreamp Second Pole Effect  Ideal Case: o Open Loop Amplifier has  Infinitive gain  Infinitive bandwidth o Ideal Dominant Pole Constant  � � � o Ideal Sensitivity  ���,����� � �  Finite DC Gain (g m1 ∙R L ≈400) � � � o Dominant Pole Constant  � �� � � � � � � � �� o Second Pole Constant  � � � o Sensitivity  ��� ���,����� ���,����� ���∙ �� � �� ∙ ���∙�� ATLAS MDT ASD DESIGN REVIEW 5/26/17 11 of 26

ASDv4 CSPreamp Transient Noise Model ATLAS MDT ASD DESIGN REVIEW 5/26/17 12 of 26

ASDv4 CSPreamp Loop Gain ATLAS MDT ASD DESIGN REVIEW 5/26/17 13 of 26

ASDv4 CSPreamp Frequency Responses ATLAS MDT ASD DESIGN REVIEW 5/26/17 14 of 26

ASDv4 CSPreamp Design Parameters Summary ATLAS MDT ASD DESIGN REVIEW 5/26/17 15 of 26

ASDv4 Outline  Channel Block Scheme  Charge Sensitive Preamplifier  Differential Amplifiers   Wilkinson ADC  Measurements Summary  Conclusion ATLAS MDT ASD DESIGN REVIEW 5/26/17 16 of 26

ASDv4 Differential Amplifiers Smaller CMFB MOS:  Reduce CSPreamp Parasitic Capacitance Load  Manage Peaking Time Delay ATLAS MDT ASD DESIGN REVIEW 5/26/17 17 of 26

ASDv4 Differential Amplifiers  5MHz center frequency  30kHz high-pass frequency  +6dB/octave slope ATLAS MDT ASD DESIGN REVIEW 5/26/17 18 of 26

ASDv4 Outline  Channel Block Scheme  Charge Sensitive Preamplifier  Differential Amplifiers  Wilkinson ADC   Measurements Summary  Conclusion ATLAS MDT ASD DESIGN REVIEW 5/26/17 19 of 26

ASDv4 Wilkinson ADC  Gain Stages Optimization o Reduction Parasitic Capacitance o Symmetrical Layout ATLAS MDT ASD DESIGN REVIEW 5/26/17 20 of 26

ASDv4 Outline  Channel Block Scheme  Charge Sensitive Preamplifier  Differential Amplifiers  Wilkinson ADC  Measurements Summary   Conclusion ATLAS MDT ASD DESIGN REVIEW 5/26/17 21 of 26

ASDv4 Measurements Summary (1/2) Fig. 2 – MDT-ASDv4 Chip Photo. Fig. 3 – DA 3 Output Signal vs. Input Charge. Fig. 5 – Peaking Time Delay vs. Input Charge. Fig. 4 – Channel Sensitivity vs. Input Charge. ATLAS MDT ASD DESIGN REVIEW 5/26/17 22 of 26

ASDv4 Measurements Summary (2/2) Fig. 7 – W-ADC Output Pulse Width vs. Input Charge. Fig. 6 – W-ADC, DA 3 Output Signals vs. Input Charge. ATLAS MDT ASD DESIGN REVIEW 5/26/17 23 of 26

ASDv4 Outline  Channel Block Scheme  Charge Sensitive Preamplifier  Differential Amplifiers  Wilkinson ADC  Measurements Summary  Conclusion  ATLAS MDT ASD DESIGN REVIEW 5/26/17 24 of 26

ASDv4 Conclusion  MDT-ASDv4 o Management of 60pF-C D o Accurate q IN -to-V conversion o Maximum Peaking Time Delay  12ns o Linear V-to-T conversion o Area of 6.38mm 2 Total Current Consumption 162mA Channel 1 Current Consumption 18.7mA* Channel 2 Current Consumption 12.56mA Total Power Consumption 535mW @3.3V of Supply Voltage Channel 1 Power Consumption 61.9mW @3.3V of Supply Voltage Channel 2 Power Consumption 41.44mW @3.3V of Supply Voltage * 32.7% LVDS Fig. 8 – MDT-ASDv4 Pin Table (70 Pins). 21% CSP 20.2% Wilkinson ADC 16% DAi i=1,2,3,4 chain 6.5% DISC1 1 Including CSP+DA1+DA2+DA3+DA4+DISC1+WILKINSON ADC+MUX+LVDS 2 Including CSP+DA1+DA2+DA3+DA4+DISC1+WILKINSON ADC ATLAS MDT ASD DESIGN REVIEW 5/26/17 25 of 26

ASDv4 Conclusion – Measurements Issues 1. Substrate Noise 2. Channel Mismatch 3. Smaller Deadtime Range ATLAS MDT ASD DESIGN REVIEW 5/26/17 26 of 26