In Search of Lost Time Andrew B. Kahng UCSD CSE and ECE Departments - PowerPoint PPT Presentation

In Search of Lost Time Andrew B. Kahng UCSD CSE and ECE Departments abk@ucsd.edu http://vlsicad.ucsd.edu TAU-2016 Friday keynote, Santa Rosa 1 A. B. Kahng, TAU 2016

In Search of Lost Time 2 A. B. Kahng, TAU 2016

What is Time? How do we lose Time? How do we regain Time? 3 A. B. Kahng, TAU 2016

What is Time? 4 A. B. Kahng, TAU 2016

What is Time? • Time = Schedule • Moore’s Law: 1% = 1 week • Time = Things convertible to time • mV, σ , uW, nm, $, µ m 2 Margin nm, mV, {skew, jitter, OCV…} Time power, area, f max , I ddq ,… rms, %, σ Model and Product Quality Analysis Accuracy 5 A. B. Kahng, TAU 2016

What is Time? • Time = Schedule • Moore’s Law: 1% = 1 week • Time = Things convertible to time • mV, σ , uW, nm, $, µ m 2 • Time = time itself • Flavors: slack, trans, xd, d-trans, … 6 A. B. Kahng, TAU 2016

What is Time? • Time = Schedule • Moore’s Law: 1% = 1 week • Time = Things convertible to time • mV, σ , uW, nm, $, µ m 2 • Time = time itself • Flavors: slack, trans, xd, d-trans, … Time = Money 7 A. B. Kahng, TAU 2016

What is Time? How do we lose Time? 8 A. B. Kahng, TAU 2016

How Do We Lose Time? • It’s tough not to … 9 A. B. Kahng, TAU 2016

Context I: Race to End of Roadmap • Paper model to v1.0 SPICE model: ~12 months @N10 • Many near-term “red bricks”: ArF, Cu, low-k, … • Foundry-fabless dynamics: who gives up margin ? • Time constants limit design-manufacturing co-evolution (Years) Tech development, app market definition, architecture/front-end design • Model-hardware these time constants Mismatches among (Months) RTL-to-GDS implementation, miscorrelation reliability qualification • Model guardbanding (Weeks) Fab latency, cycles of yield learning, • Faster node enablement design re-spins, mask flows is challenging !! (Days) Process tweaks, design ECOs 10 A. B. Kahng, TAU 2016

Context II: Low-Power Grand Challenge Green datacenters Cloud Big data Low power = High complexity multiple supply voltages, power and clock gating, DVFS, MTCMOS, Mobility multi-Lgate, … Internet of Things Increased timing closure burden 11 A. B. Kahng, TAU 2016

How Do We Lose Time? • It’s tough not to … • The margining imperative … 12 A. B. Kahng, TAU 2016

Nobody Wants to Own the Scrap • Timing model not 100% accurate • Add margin to cover unknowns 13 A. B. Kahng, TAU 2016

 Stacks of Margins Design margin = stack of layers of conservatism Reliability Temperature Voltage Process Nominal Vdd PDF Signoff Static IR drop Signoff Power grid IR gradient Dynamic IR HCI/NBTI performance Signoff source: Wu 08 14 A. B. Kahng, TAU 2016

 Consequences • Diminishing ROI from next node • Typical: Moore’s Law-like scaling • Worst-case: scales, but worse ROI • Signoff with excessive margin: potential gain wiped out 15 A. B. Kahng, TAU 2016

Time: Lose Some, Win Some 90 nm 65 nm 45/40 nm 28 nm 20 nm 16/14 nm 10 nm ≤ 7 nm Multi- Temp MOL, BEOL R ↑ Maxtrans Dynamic IR patterning patterning inversion PBA Fixed-margin MIS Noise spec EM Cell-POCV MCMM Phys-aware AOCV / Min timing ECO POCV implant LVF BTI BEOL, MOL variations Signoff criteria with AVS SOC complexity Fill effects Layout rules 16 A. B. Kahng, TAU 2016

How Do We Lose Time? • It’s tough not to … • The margining imperative … • We give it away c2q-setup-hold surface • Intentionally 17 A. B. Kahng, TAU 2016

How Do We Lose Time? • It’s tough not to … • The margining imperative … • We give it away • Intentionally Homogeneous BEOL Interconnect stack with M1 and M2 corners (e.g., Cworst) Homogeneous M2 C C w corner Layer M2 3 σ Pessimism -3 σ 3 σ C M1 C Layer M1 3 σ -3 σ C 18 A. B. Kahng, TAU 2016

How Do We Lose Time? • It’s tough not to … • The margining imperative … • We give it away 0.1 • Intentionally 0 T 2 Path Slack (ns) -0.1 • By miscorrelating -0.2 -0.3 -0.4 123 ps -0.5 -0.6 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 T 1 Path Slack (ns) 19 A. B. Kahng, TAU 2016

How Do We Lose Time? • It’s tough not to … • The margining imperative … • We give it away • Intentionally • By miscorrelating • By wasting it 2013 Contest NDA: Without [EDA vendor’s] prior approval, I shall not write or publish any article or presentation that references [EDA vendor’s tool name]. 20 A. B. Kahng, TAU 2016

How Do We Lose Time? • It’s tough not to … • The margining imperative … • We give it away • Intentionally • By miscorrelating • By wasting it “We don’t have enough time to do it right, but we have enough time to do it wrong” 21 A. B. Kahng, TAU 2016

Not Enough Time To Do It Right… Option #1: go with latest available technology = 0.01 AU/year speed Option #2: Need a faster ship spend the next ten years to come up with a spaceship = 0.1 AU/year speed Year: 2016 2026 2027 2031 • Earth to Mars Option #1 = 0.5 / 0.01 = 50 years Option #2 = 0.5 / 0.1 + 10 years = 15 years (B<< A) • Issue: investment for the long haul Option #1 Option #2 Corner-based STA Statistical STA Planar 3D Homogeneous CMOS Heterogeneous CMOS 22 A. B. Kahng, TAU 2016

What is Time? How do we lose Time? How do we regain Time? 23 A. B. Kahng, TAU 2016

How Do We Regain Time? • Learn !!! (machine learning, Big Data mindset) 24 A. B. Kahng, TAU 2016

[DATE14] Timer Miscorrelation 0.1 0 T 2 Path Slack (ns) -0.1 -0.2 -0.3 123 ps -0.4 -0.5 -0.6 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 T 1 Path Slack (ns) • T 1 and T 2 : commercial signoff STA tools with same inputs (.v, .spef, .lib) • 123ps slack divergence  20% performance difference  one node of Moore’s Law scaling 25 A. B. Kahng, TAU 2016

[DATE14] Erase Miscorrelation with Machine Learning! Can also erase INCREMENTAL If Outliers error > P&R vs. signoff (data points) threshold STA miscorrelation New Designs MODELS Train Validate Test (Path slack, setup time, stage, cell, wire delays) Artificial Real Circuits Designs ONE-TIME AFTER BEFORE 0.1 0 T 2 Path Slack (ns) T 2 Path Slack (ns) -0.1 -0.2 ML 31 ps -0.3 Modeling ~4 × reduction -0.4 123 ps -0.5 -0.6 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 T 1 Path Slack (ns) T 1 Path Slack (ns) 26 A. B. Kahng, TAU 2016

[SLIP15] Harder: Non-SI to SI Calibration • Complex interplay of electrical, Post P & R Database logic structure, and layout parameters .v .v .sdc .spef .db, .lib • Black-box code in STA tools • Slack diverges by 81ps (clock period = 1.0ns) • ~4 stages of logic at 28nm FDSOI Non-SI Timing Non-SI Timing Report Report Non-SI Path Slack (ns) ($) Calibration: Recipe to Convert Non-SI Timing Report to SI Timing Report 81ps SI Timing SI Timing Report Report SI Timing Report SI Path Slack (ns) ($$$) 27 A. B. Kahng, TAU 2016

[SLIP15] “SI for Free” with Machine Learning Timing Reports Timing Reports in • Machine learning of in SI Mode Non-SI Mode incremental transition Create Training, Validation and Testing Sets time, delay due to SI ANN (2 Hidden Layers, SVM (RBF Kernel, 5-Fold • Accurate SI-aware 5-Fold Cross-Validation) Cross-Validation) path delays, slacks HSM (Weighted Predictions from ANN and SVM) Save Model and Exit BEFORE AFTER Non-SI Path Slack (ns) ($) Predicted Path Delay (ps) Worst absolute 81ps error = 8.2ps Average absolute ML 8.2ps error = 1.7ps Modeling SI Path Slack (ns) ($$$) 28 Actual Path Delay (ps) A. B. Kahng, TAU 2016

[ASPDAC16] Similar: Closing Multiphysics Analysis Loops Sim Results (Dyn.) Activity Functional Tech files, signoff Sim vectors Sim Factor (Static) criteria, corners Benchmark RTL IR Drop Power Thermal Map AVS Trace Analysis Power Timing / Temp Analysis Glitches Map Slack Task Mapping/ Timing/ Migration/ P&R + Noise Reliability (DVFS) Optimization Report MTTF & Aging 29 A. B. Kahng, TAU 2016

[ASPDAC16] Similar: Closing Multiphysics Analysis Loops Sim Results Workload-Thermal loop (Dyn.) Activity Functional Tech files, signoff Sim vectors Sim Factor (Static) criteria, corners Benchmark STA-IR loop RTL IR Drop Power Thermal Map AVS Trace Analysis Power Timing / Temp Analysis Glitches Map Slack Task Mapping/ Timing/ Migration/ P&R + Noise Reliability (DVFS) Optimization STA-Thermal Report loop MTTF & Aging STA-Reliability loop 30 A. B. Kahng, TAU 2016

[ASPDAC16] Multiphysics Analysis is Difficult to Predict • IR drop, thermal, reliability, crosstalk, etc. • Example: Can we predict “risk map” for embedded memories at floorplan stage ? SRAM Slack (ps) 29ps 25ps SRAM #1 SRAM #5 31 A. B. Kahng, TAU 2016

[ASPDAC16] Multiphysics Analysis is Difficult to Predict • IR drop, thermal, reliability, crosstalk, etc. • Example: Can we predict “risk map” for embedded memories at floorplan stage ? SRAM Slack (ps) Implementation Index 32 A. B. Kahng, TAU 2016