Improving NAND Endurance by Dynamic Program and Erase Scaling - PowerPoint PPT Presentation

1 Improving NAND Endurance by Dynamic Program and Erase Scaling Jihong Kim Department of Computer Science and Engineering Seoul National University, Korea NVRAMOS 2013 October 24, 2013

Trend 1 : NAND Capacity +2x / 2 years Capacity (2000~2012 ISCC, VLSI) SLC (1 bit/cell) MLC (2 bits/cell) TLC (3 bits/cell) 2000 2002 2004 2006 2008 2010 2012 2014 Year The cost-per-bit of NAND devices is continuously improving. 2 / 31

Trend 2 : NAND Endurance Endurance Capacity +2x / 2 years -70% / 4 yrs 2000 2002 2004 2006 2008 2010 2012 2014 Year The NAND endurance is drastically decreased last 4 years as a side effect of recent advanced technologies. 3 / 31

Trend 3 : Total Amount of Writes Total amount of writes = Endurance X Capacity Total amount of writes Capacity +2x / 2 years Endurance -70% / 4 years 2002 2004 2006 2008 2010 2012 2014 Year The total amount of writes of NAND-based storage does not increase as much as we expected. 4 / 31

Trend 4 : Lifetime of NAND-Based Storages Lifetime = Endurance X Capacity Lifetime Wday X WAF Capacity Total amount of writes Endurance 2002 2004 2006 2008 2010 2012 2014 Year 5 / 31

Existing Lifetime Enhancing Schemes 𝐹𝐹𝐹𝐹𝐹𝐹𝐹𝐹𝐹 × 𝐷𝐹𝐷𝐹𝐹𝐷𝐷𝐷 𝑀𝐷𝑀𝐹𝐷𝐷𝑀𝐹 = 𝑋 × 𝑋𝑋𝑋 𝑒𝑒𝑒 Reducing WAF by increasing the ① Data compression efficiency of an FTL algorithm ② Deduplication (e.g., garbage collection, ③ Dynamic throttling wear leveling) 6 / 31

Our Goal Endurance X Capacity Lifetime = Lifetime Wday X WAF Capacity Total amount of writes Our goal By improving the NAND endurance. Endurance 2002 2004 2006 2008 2010 2012 2014 Year Improving the NAND endurance is required for sustainable growth in the NAND flash-based storage market. 7 / 31

Outline • Introduction • Motivation • Key Components of the DPES Approach Erase Voltage Scaling • Program Time Scaling • Dynamic Program and Erase Scaling • • Implementation of DPES-Aware FTL • Experimental Results • Conclusion 8 / 31

Motivation : Device Physics Model Cross-section view of NAND flash memory cells Bit Errors ECC Program voltage Limit P/E Cycles Control Gate NAND endurance Floating Gate Erase voltage Tunnel Oxide Substrate Endurance Erase voltage 9 / 31

Overview of Our Proposed Approach DPES (Dynamic Program and Erase Scaling) approach Erase voltage/time scaling ( Tradeoff : endurance and erase voltage/time ) Program time scaling ( Tradeoff : erase voltage and program time ) Dynamically changes program and erase voltage/time Improves the NAND endurance without degradation in the overall write throughput 10 / 31

Outline • Introduction • Motivation • Key Components of the DPES Approach Erase Voltage Scaling • Program Time Scaling • Dynamic Program and Erase Scaling • • Implementation of DPES-Aware FTL • Experimental Results • Conclusion 11 / 31

Erase Voltage Scaling “Effective wearing represents the effective degree of NAND wearing after one P/E cycle.” 1.5 1.5 Average retention BER Effective wearing r = 0.00 (normalized) r = 0.07 1.0 1.0 r = 0.14 0.5 0.5 0.0 0.0 1.00 0.95 0.90 0.85 0.80 0 1 2 3 4 Normalized erase voltage (1- r ) Number of P/E cycles [K] Lowering the erase voltage can reduce the effective wearing. 12 / 31

Effect of Erase Voltage Scaling Total sum of Endurance effective wearing 3K P/E 3.00 K 3.00 K 6.52 K 1.38 K Effective wearing / one P/E effective wearing 1.00 0.46 Total sum of 3.00K 1.38K ~ 2x increase 1.00 x 0.86 x 3.00K 6.52K Erase Voltage P/E Cycles 13 / 31

Writing Data to a Shallowly Erased Block ∝ Erase voltage Width of Vth distributions V ERASE (nominal) Width of Vth distributions Saved Vth margin V ERASE (small) Width of Vth distributions To write data to a shallowly erased NAND block, it is necessary to shorten the width of Vth distributions. 14 / 31

Program Time Scaling Tradeoff : {Program time} vs. {Width of Vth distributions} Incremental Step Pulse Program Scheme Step voltage 3 2 1 Width of Vth distributions Program time Step voltage 1 2 3 4 5 Width of Vth distributions Program time To shorten the width of Vth distributions, the program time is increased. 15 / 31

Minimum Program Time Requirement Erase voltage mode : 𝑭𝑭𝑭𝑭𝑭𝑭 𝒋 Program Erase 𝒍 ≥ 𝒋 State State Write mode : 𝑿𝑭𝑭𝑭𝑭 𝒍 Minimum Program time 2.0 2.0 𝑭𝑭𝑭𝑭𝑭𝑭 𝟓 𝑿𝑭𝑭𝑭𝑭 𝟓 Program time (normalized) (normalized) 𝑿𝑭𝑭𝑭𝑭 𝟒 𝑭𝑭𝑭𝑭𝑭𝑭 𝟒 1.5 1.5 𝑿𝑭𝑭𝑭𝑭 𝟑 𝑭𝑭𝑭𝑭𝑭𝑭 𝟑 𝑿𝑭𝑭𝑭𝑭 𝟐 𝑭𝑭𝑭𝑭𝑭𝑭 𝟐 1.0 1.0 0.00 0.20 0.40 0.60 1.00 0.95 0.90 0.85 𝑿𝑭𝑭𝑭𝑭 𝟏 𝑭𝑭𝑭𝑭𝑭𝑭 𝟏 V ISPP scaling ratio Normalized erase voltage (1- r ) ( ∝ 𝑻𝑻𝑻𝑭𝑭 𝑭𝑾𝑾 𝑭𝑻𝒏𝒏𝒋𝒏 ) 16 / 31

Example of EVmode and Wmode Selection Example of erase voltage modes Example of write modes 𝑭𝑭𝑭𝑭𝑭𝑭 𝟏 𝑿𝑭𝑭𝑭𝑭 𝟏 𝑭𝑭𝑭𝑭𝑭𝑭 𝟐 𝑿𝑭𝑭𝑭𝑭 𝟐 𝑭𝑭𝑭𝑭𝑭𝑭 𝟑 𝑿𝑭𝑭𝑭𝑭 𝟑 𝑭𝑭𝑭𝑭𝑭𝑭 𝟒 𝑿𝑭𝑭𝑭𝑭 𝟒 𝑭𝑭𝑭𝑭𝑭𝑭 𝟓 𝑿𝑭𝑭𝑭𝑭 𝟓 Vth voltage margin Vth distribution erased with 𝑭𝑭𝑭𝑭𝑭𝑭 𝟑 For writing a block erased with 𝑭𝑭𝑭𝑭𝑭𝑭 𝟑 , 𝑿𝑭𝑭𝑭𝑭 𝟑 , 𝑿𝑭𝑭𝑭𝑭 𝟒 , 𝑿𝑭𝑭𝑭𝑭 𝟓 should be used. 17 / 31

Lazy Erase Scheme Program 𝑿𝑭𝑭𝑭𝑭 𝟏 state Erasing with 𝑭𝑭𝑭𝑭𝑭𝑭 𝟑 . Shallow erase Erase 𝑭𝑭𝑭𝑭𝑭𝑭 𝟑 state To write data with a faster write mode (e.g., 𝑿𝑭𝑭𝑭𝑭 𝟏 ) to the shallowly erased block, Erase Lazy erase 𝑭𝑭𝑭𝑭𝑭𝑭 𝟏 state Writing with 𝑿𝑭𝑭𝑭𝑭 𝟏 Program 𝑿𝑭𝑭𝑭𝑭 𝟏 state 18 / 31

Dynamic Program and Erase Scaling Program times and erase voltages are dynamically changed for improving the NAND endurance . Minimum Wearing program time High DPES- erase voltage Enabled mode High damage Short NAND Chip • • • Low erase voltage Low damage mode Long DPES enables S/W to exploit the tradeoff relationship between the NAND endurance and the erase voltage/time. 19 / 31

Outline • Introduction • Motivation • Key Components of the DPES Approach Erase Voltage Scaling • Program Time Scaling • Dynamic Program and Erase Scaling • • Implementation of DPES-Aware FTL • Experimental Results • Conclusion 20 / 31

Overview of DPES-Aware FTL (AutoFTL) Write Request DPES Manager Garbage Collector Number of Circular NAND Endurance pages Buffer Model Background to be copied Foreground Utilization Mode Wmode Emode Wear Selector Selector Selector Leveler Wmode i EVmode j , ESmode k Extended Mapping Table NAND Logical-to-Physical Per-Block Mode Table Setting Table Mapping Table DeviceSettings Program Erase Read NAND Flash Memory 21 / 31

AutoFTL : Write Mode Selection The DPES manager chooses the most appropriate write mode depending on the buffer utilization ratio. [ Write-mode selection rules ] head Dequeue Program Buffer utilization Write time ( u ) mode K-entry u ≤ 20% 4 circular 3 20% < u ≤ 40% buffer 2 40% < u ≤ 60% 1 60% < u ≤ 80% Enqueue tail u > 80% 0 Short idle times Long idle times Requests 22 / 31

DPES-Aware Write and Read Operations Address Logical Physical Translation Address Address Table DPES Write/read NAND Block_Addr Block_Addr Manager Request Chips Per-Block set mode Mode Table Device Setting for mode write write write read read 3 2 (3) (3) (3) (2) (2) Read/Verify references, time ISPP voltages, (Erase voltage) Time overhead << T PROG 23 / 31

AutoFTL : Erase Voltage Mode Selection 𝑭𝑭𝑭𝑭𝑭𝑭 𝒋 = ? Program Erase 𝑮𝑮𝑾𝑮𝒏𝑭 𝑮𝑾𝒋𝒗𝒋𝒗𝑻𝑾𝒋𝑭𝒏 𝑭𝒑 𝒅𝒋𝒏𝒅𝑮𝒗𝑻𝒏 𝒄𝑮𝒑𝒑𝑭𝒏 State State Future : 𝑿𝑭𝑭𝑭𝑭 𝒍 If we know 𝑿𝑭𝑭𝑭𝑭 𝒍 If we don’t know 𝑿𝑭𝑭𝑭𝑭 𝒍 before a block is erased before a block is erased Background garbage collection, Cases Foreground garbage collection wear leveling Prediction based on the past utilization history 𝑭𝑭𝑭𝑭𝑭𝑭 𝒋 𝒋 = 𝒍 Incorrect prediction  Lazy erase 24 / 31

AutoFTL : DPES-Aware Garbage Collection Page copy with 𝑿𝑭𝑭𝑭𝑭 𝒍 Victim Free block block ∆𝑮 𝒅𝑭𝒅𝒅 Circular Circular Buffer Buffer Current utilization, 𝑮 Effective utilization, 𝑮 𝑭 = 𝑮 + ∆𝑮 𝒅𝑭𝒅𝒅 25 / 31

Outline • Introduction • Motivation • Key Components of the DPES Approach Erase Voltage Scaling • Program Time Scaling • Dynamic Program and Erase Scaling • • Implementation of DPES-Aware FTL • Experimental Results • Conclusion 26 / 31