IEEE EMC Society Distinguished Lecturer Seminar: IEEE EMC Society Distinguished Lecturer Seminar: IEEE EMC Society Distinguished Lecturer Seminar: IEEE EMC Society Distinguished Lecturer Seminar: Signal Integrity of TSV-Based 3D IC Signal Integrity of TSV-Based 3D IC July 21 2010 July 21, 2010 Joungho Kim at KAIST joungho@ee kaist ac kr joungho@ee.kaist.ac.kr http://tera.kaist.ac.kr TERA 1 Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory
Contents 1) Driving Forces of 3D Package and IC 2) Signal Integrity Design 3) 3) N i Noise Coupling Issues C li I 4) Noise Isolations 5) Summary TERA 2 Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory
3D Movie 3D Movie TERA 3 Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory
3D Housings 3D Housings Sk Sky Lounge L Apartment Medical care center Restaurant Fitness & Spa Fitness & Spa Parking TERA 4 Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory
16GB Samsung NAND Flash, 8Gbx16 16GB Samsung NAND Flash, 8Gbx16 TERA 5 Terahertz Interconnection and Package Laboratory Sharp, Morihiro Kada Terahertz Interconnection and Package Laboratory
3D Hamburger 3D Hamburger SDRAM Di it l C Digital Core Analog RF TERA 6 Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory 6
Expected Market of 3D IC Expected Market of 3D IC Market Driving Forces of 3D IC “More than Moore” Heterogeneous integration � Co-integration of RF + logic + Performance memory + sensors in a reduced space driven Electrical performance Electrical performance � ”Mid t � ”Mid term” ” driver: > 2010 � Interconnect speed and reduced parasitic power DRAM Logic consumption MEMS 3D vs. “More Moore” � Can 3D be cheaper 3D IC 3D IC than going to the next RF- lithography node? Optimum Market Optimum Market SiP SiP Access Conditions Access Conditions CIS Cost Form factor Flash Density (NAND & NOR) � Achieving the highest driven driven driven driven � “Long term” � Long term capacity / volume ratio driver: > 2012 � “Short term” driver: > 2008 Source: “3D IC & TSV Report” Yole Development Source: 3D IC & TSV Report , Yole Development TERA 7 Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory
Technology Trend of 3D IC Technology Trend of 3D IC * ref: IBM J. RES. & DEV. VOL. 52 NO.6 NOVEMBER 2008, * f IBM J RES & DEV VOL 52 NO 6 NOVEMBER 2008 O per cm 2 ) p555 3D-I C integration I/O: 0.4 - 10.0 μ m pitch 10 5 – 10 8 I/O per cm 2 ranges (I / O Wiring pitch: 45nm Wiring pitch: 45nm tch, and Si-on-Si package and chip stacking p g tion density pitch, I / O pi I/O: 10-50 μ m pitch 10 3 - 10 6 I/O per cm 2 Wiring pitch: 0.5 μ m ive wiring p nterconnect Organic and ceramic package (SCM and MCM) I/O: 200 μ m pitch I/O: 200- μ m pitch I / O in Relati 10 2 - 10 3 I/O per cm 2 Wiring pitch: 25 - 200 μ m 2000 2010 Time Relative comparison of I / O densities for 3D silicon, 3D die stacking, Relative comparison of I / O densities for 3D silicon, 3D die stacking, and silicon packaging, for both ceramic and organic packaging TERA 8 Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory
Core Technologies of 3D IC Core Technologies of 3D IC Su Substrate Attach Attachment nt TSV TSV Via Vi Unified Unified Ball Ball PCB PCB Design/CAD Design/CAD Design/CAD Design/CAD Environment Environment and Test and Test 3D Thermal 3D Thermal Chip & SoC Chip & SoC & Reliability Analysis & Reliability Analysis Architecture and Architecture and And Design And Design Design Methodologies Design Methodologies Design Methodologies Design Methodologies Methodologies Methodologies 3D IC 3D IC 3D IC 3D IC Low Cost Interposer Low Cost Interposer p Chip Chip-to p to- -Wafer Wafer Process and Design Process and Design Stacking & Bonding, Stacking & Bonding, Technology Technology TSV Technology TSV Technology TERA 9 9 Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory
Signal Integrity Design Issues in 3D IC Signal Integrity Design Issues in 3D IC Signal Integrity I: Signal Integrity I: Signal Integrity II: Signal Integrity II: Loading Effect & Reflection Loading Effect & Reflection Crosstalk & Jitter Crosstalk & Jitter 3D IC using TSV g Port 1 (Through Silicon Via) Ground via Signal via Ground via ( ) 0 C ox C ox S21(Phase) [Degree] SiO2 C sil C sil -10 C via_ox C via_ox C via_ox C via_ox -20 L via G sil L via G sil L via Si G sil G sil -30 R via R via R via Solid line = model Symbol line = measurement CIS -40 C via_ox C via_ox C via_ox C via_ox C sil C sil 0.1 1 10 20 Frequency [GHz] C ox C C C ox Port 2 Logic - Limitation of High Speed Signaling - Crosstalk Between TSVs by Capacitive Loading - Die-to-Die Vertical Coupling - Impedance Mismatching, Reflection - Jitter by Inter-Symbol-Interference Analog RF DRAM Si-Interposer p EMI EMI Power Integrity Power Integrity Power Integrity Power Integrity DSP Chip 7 V SSN Chip 6 Chip 5 Through Through- Power Power Chi Chip 4 4 wafer via Chip 3 Chip 2 Chip 1 Ground - Vertical Die-to-Die EMI Coupling Vertical Die to Die EMI Coupling - Simultaneous Switching Noise caused Simultaneous Switching Noise caused - RF Sensitivity Reduction by EMI by Insufficient Power - EM Radiation Increase - High freq Noise Coupling & Transfer TERA 10 Terahertz Interconnection and Package Laboratory 10 Terahertz Interconnection and Package Laboratory
Disadvantages of Wire Bonding Stacked Chip Package Disadvantages of Wire Bonding Stacked Chip Package • Long Interconnection � Long RC Delays � High Impedance for Power Distribution Network � Hi h P � High Power Consumption C ti � Poor Heat Dissipation (Thick Substrate) • Bonding Wire located in Chip Perimeter � Low Density Chip Wiring � Limited Number of I/O � Limited I/O Pitch � Large Area Package 3D Stacked Chip Package with Wire Bonding • Complex Interposer � Long Redistribution Interconnection � Bonding Wire located in Interposer Periphery TERA 11 Terahertz Interconnection and Package Laboratory 11 Terahertz Interconnection and Package Laboratory
Key Technology : TSV (Through Silicon Via) Key Technology : TSV (Through Silicon Via) • Short Interconnection � Reduced RC Delays � Low Impedance for Power Distribution Network � Low Impedance for Power Distribution Network � Low Power Consumption 3 rd Chip � Heat Dissipation Through Via (Thinned Substrate) Under fill Dielectric 2 nd Chip (Thinned • No Space Limitation for Interconnection p Substrate) Substrate) � High Density Chip Wiring Dielectric � No Limitation of I/O Number Under fill � No Limitation of I/O Pitch Multi-level � Small Area Package S a ea ac age On chip Interconnect On-chip Interconnect 1 st Chip SiO2 Si-Substrate 3D TSV Stacked IC TERA 12 Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory
★ W hy does TSV Fam ily happy ^ ^ ? Happy TSV Fam ily~ ! Elevator !! Sad W ire-bonding Fam ily~ ! So fast! ♬ ♬ So fast! It’s awesome!! 4 th Floor So tired T^T ! It takes too much • Shorter distance ! energy !! • Lower loss of energy ! 3 rd Floor Stairs !! Stairs !! T^T T0T 2 nd Floor ^^ ^^ 1 st Floor TERA 13 Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory
10 chip stacked Package by KAIST 10 chip stacked Package by KAIST 10 9 8 7 6 5 4 3 2 1 55 μ m TSV diameter 150 μ m Pitch TERA 14 Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory
Background(1): High-frequency Channel Loss in TSV Background(1): High-frequency Channel Loss in TSV G G sil -Significant high-frequency signal loss occur at Signal Transmission Through TSV Significant high frequency signal loss occur at Signal Transmission Through TSV C via_ox -The signal loss through TSV is caused by substrate leakage and coupling 0.1 μ m dB] gnitude ) [d S21(mag Frequency [GHz] Si SiO 2 Ta Cu Close up of through wafer via Magnitude of S21 TERA 15 Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory
Background(2): Increased Channel Loss in Multi-Stack TSV Background(2): Increased Channel Loss in Multi-Stack TSV -Signal loss increases substantially with number of stacks/TSVs -The signal loss through TSV is caused by substrate leakage and coupling Th i l l h h TSV i d b b l k d li Increased Total Resistance Increased Total Capacitance (Slopes) 10 10 9 2-Stack TSVs 8 7 5-Stack TSVs 6 5 5 4 10-Stacked TSVs 3 2 1 TERA 16 Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory
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