I s today’s I s today’s I s today s I s today s design m ethodology design m ethodology a recipe for a a recipe for a a recipe for a a recipe for a Tacom a Narrow s incident? Tacom a Narrow s incident? Carl Seger Carl Seger Strategic CAD Labs Strategic CAD Labs I ntel Corporation I ntel Corporation July July 8 , l 8 , 2 0 0 9 2 0 0 9 2 0 0 9 2 0 0 9
Outline Outline Outline Outline Validation brick w all Validation brick w all Validation brick w all Validation brick w all Tw o types of validation Tw o types of validation W hat is know n W hat is know n W hat is know n W hat is know n – More developm ent needed More developm ent needed W hat is unknow n W h t i W h t i W hat is unknow n k k – More research neede More research neede Danger of “business as usual” Danger of “business as usual” 2
Electronic Circuits Electronic Circuits Electronic Circuits Electronic Circuits Moore’s law drives industry Moore’s law drives industry – Num ber of transistors available Num ber of transistors available b b f f i i il bl il bl doubles every tw o years doubles every tw o years – Over Over 2 2 billion in billion in 2 0 0 9 2 0 0 9 – No sign of show – No sign of show No sign of show -stoppers for No sign of show -stoppers for stoppers for stoppers for next next 1 0 1 0 - -1 5 1 5 years. years. Extrem ely com plex system s Extrem ely com plex system s can be designed on a single can be designed on a single can be designed on a single can be designed on a single die die – Single chip m ulti Single chip m ulti- -core core p processors processors – System On a Chip System On a Chip Society increasingly depends Society increasingly depends on correctly functioning on correctly functioning y y g g products and devices products and devices 3
Design Challenges Design Challenges Design Challenges Design Challenges Out-of-order, threading, In-order, pipelined mcode-fusion, power mgmt, … Com plexity of design Com plexity of design More transistors → More transistors → – More transistors More transistors More functionality → More functionality More design effort More design effort Num ber & size of m odels 2,500,000 Num ber & size of m odels Lines of RTL L 2 000 000 2,000,000 – Perform ance, ERTL, GRTL, P P Perform ance, ERTL, GRTL, f f ERTL GRTL ERTL GRTL Schem atics, … Schem atics, … 1,500,000 – Multi Multi- -m illion line RTL m illion line RTL 1,000,000 500,000 8000 4000000 Multi Multi objective convergence Multi Multi-objective convergence objective convergence objective convergence 0 7000 3500000 P4 P5 P6 WMT NWD PSC – Tim ing, pow er, area, etc. Tim ing, pow er, area, etc. Files 6000 3000000 feedback w ay too late in feedback w ay too late in Checked In 5000 design schedules design schedules #Total 2500000 Lines 4000 2000000 # Pre-silicon bugs Lines Validation of design Validation of design Validation of design Validation of design 3000 3000 1500000 1500000 Ch Changed d Increasing rate – Bug rate rising ~ Bug rate rising ~ 4 4 x per lead x per lead (~4x per lead) 2000 1000000 – Trillions of sim ulation cycles Trillions of sim ulation cycles 1000 500000 on a rapidly changing m odel on a rapidly changing m odel 486 P5 P6 WMT NHM 0 0 1996-02 1996-04 1996-06 1996-08 1996-10 1996-12 1997-02 1997-04 1997-06 1997-08 1997-10 1997-12 1998-02 1998-04 1998-06 1998-08 1998-10 1998-12 1999-02 1999-04 1999-06 1999-08 1999-10 1999-12 2000-02 2000-04 2000-06 2000-08 2000-10 2000-12 2001-02 2001-04 Analyze Plan Design 4 weeks/months
Verification Verification Without major breakthroughs, verification will be a non-scalable, show-stopping barrier to further , pp g Brick W all Brick W all Brick W all Brick W all progress in the semiconductor industry THE INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS: 2005/6 Verification killing schedules Too many pre-Si bugs! N. America Re-spin Statistics 1 0 0 0 0 on success on success 8 0 0 0 48% 44% 39% 6 0 0 0 st silico silico 4 0 0 0 71% of SoC re-spins 2 0 0 0 due to logic bugs 1 st 0 2002 1999 2004 Source:* 2002 Collett International Research and Synopsys Bugs found too late Pre-Si validation headcount growing fast Incoming bugs (5 wks AVG) Validation HC 80 70 60 50 BUG BET # of bugs 40 30 20 10 ‘02 ‘03 ‘04 ‘05 0 # WW before TO 5
Tw o Classes of Bugs: Tw o Classes of Bugs: Tw o Classes of Bugs: Tw o Classes of Bugs: Specification Specification bugs bugs – “W hat” is captured “W hat” is captured incorrectly incorrectly – Unintended interactions Unintended interactions – Com m unication failures Com m unication failures – Deadlock Deadlock – Livelock Livelock I m plem entation I m plem entation bugs bugs – “How ” is captured “H “How ” is captured “H ” i ” i t t d d incorrectly incorrectly – Refinem ent failed Refinem ent failed Note: N Note: N t t mentation bugs cation bugs – The m ore abstract the The m ore abstract the specification is, the m ore specification is, the m ore im plem entation bugs im plem entation bugs p p g g Specific Implem ( and vice versa) . ( and vice versa) . Abstraction Level 6
How to Address How to Address I m plem entation Bugs I m plem entation Bugs I m plem entation Bugs I m plem entation Bugs Form al equivalence* checking Form al equivalence* checking Form al equivalence Form al equivalence checking checking – Poster child of form al m ethods Poster child of form al m ethods – Sequential checking and local property Sequential checking and local property verification are still difficult and can verification are still difficult and can benefit from algorithm ic breakthroughs benefit from algorithm ic breakthroughs How ever FEV is very lim ited in How ever, FEV is very lim ited in How ever FEV is very lim ited in How ever, FEV is very lim ited in abstraction gap that can be bridged abstraction gap that can be bridged I ntegrated design and verification can I ntegrated design and verification can I ntegrated design and verification can I ntegrated design and verification can solve this problem solve this problem * Should really be called Formal Refinement Checking 7
I ntegrating Design and I ntegrating Design and Verification Verification Verification Verification Start w ith a very high Start w ith a very high- -level level Validatio m odel description of the m odel description of the m odel description of the m odel description of the n design design – Validation target Validation target Verified steps Through sequential design Through sequential design HLM steps: steps: – Create m ore detail & Create m ore detail & C C t t d t il & d t il & M1 explore/ add/ rem ove explore/ add/ rem ove – W hile proving that each W hile proving that each step m aintains correctness step m aintains correctness M2 Additionally, start from Additionally, start from d t il d d d t il d d detailed design and detailed design and i i d d M3 abstract up abstract up M3’ – Abstract details by Abstract details by transform ations transform ations GRTL – W hile proving that each W hile proving that each p p g g step m aintains correctness step m aintains correctness t t i t i i t i t t gRTL System : System : SCH – ensures correctness ensures correctness – autom atically replays steps autom atically replays steps 8
Exam ple Designs Done Using a Exam ple Designs Done Using a P otot pe I DV S stem Prototype I DV System Prototype I DV System P otot pe I DV S stem Bottom line: During 13 months of design effort, no RTL changes were needed because of implementation considerations. Top Top- -level RTL Entry level RTL Entry Early Design: RTL to Early Design: RTL to netlist netlist Final FPU pipeline diagram Final FPU pipeline diagram gclk 0 10 1 2 3 4 5 6 7 8 9 12,000 lines of RTL Read Accum ulator W rite dt_latchclosed dt_latchopen clk S SC CL L C. Seger - Intel Confidential 17 SC S CL L Front: Back: C. Seger - Intel Confidential 19 1: Control decoding and data alignment 4: FP-adder part 1 2: Partial products and CSA tree 5: FP-adder part 2 Logic And Physical View Logic And Physical View Final Design Sent to Router Final Design Sent to Router 3: CPA adder and (re-)assembly 6: Dot product 7: Rounder part 1 Outside FPU: 8: Rounder part 2 ≤ 0: Read from register file and send data 9: Rounder part 3 + re-assembly ≥ 10: Send data back to register file and write 75 130,000 trans. Graphics execution unit (2 RF + 1 CAM) (~120,000 gates) HLM -> Placed cells Converged to 270ps Clock spine Clock spine RF RF EBBs EBBs CAM EBB CAM EBB S L SC S S CL L L Keepout region Keepout region region region SC S L L L Keepout Keepout S S CL C. Seger - Intel Confidential 29 C. Seger - Intel Confidential 24 9
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