High-Speed VLSI Simulator Q I CH E N P A N ZH A N G S U P E R V - PowerPoint PPT Presentation

High-Speed VLSI Simulator Q I CH E N P A N ZH A N G S U P E R V I S O R : P R O F . S O U R A J E E T R O Y

Background  Interconnects  transmission lines, copper wires, and Carbon nano-tubes  Board to board, chip to chip, PCB, on chip level  High-speed  High frequency clock rates  Short signal rise-time  Current Challenges  Interconnect can be responsible for logic glitches, and signal delay which can render the circuit inoperable  Distributed element, tradeoffs between CPU cost and accuracy

Objective  Fall Semester  Design and develop a general purpose circuit simulator capable of CAD of high-speed interconnect  Frequency domain and time domain  Single conductor and multi conductor  Spring Semester  Reduce computation time and cost by investigating Model Order Reduction(MOR) method  Parallel simulation, wave form relaxation  Reduces the number of unknowns to significantly decrease computation time

Engineering Methods  Tools  Programs written in C++ and operates on CSU’s CRAY supercomputer  Usage of an industry standard, HSPICE, as a result reference  Mathematical Models  Modified Nodal Analysis  Partial, ODE circuit representation and solution  Lumped model representation  Matrix operations  Technical Performance Measurements  Accuracy, CPU time, and stability of the simulation results

Current Work  Budget  $0, purely software design  Responsibilities  Joint  From layout to mathematical representation (MNA)  Qi  Implement the code to simulate circuit in the time domain  Pan  Implement code to simulate circuit in the frequency domain

Interconnect Model  Telegrapher’s partial differential equation  Lumped Model

Interconnect Model Single conductor Lumped Model Multi- conductor Lumped Model

Frequency Domain Analysis  Mathematical representation  Layout to “Stamp”(MNA/ ODE model)  Laplace domain  LU decomposition & complexity

Frequency Domain Analysis  Simulation  single line interconnect, comparison to HSPICE

Frequency Domain Analysis First Trial CPU time: 92 s Second Trial CPU time: 61 s

Frequency Domain Analysis First Trial CPU time: 92 s Second Trial CPU time: 61 s

Time Domain Analysis  Mathematical representation  Using existing models from frequency domain analysis  Using implicit numerical integration methods to approximate time domain solution   C C   + = + n n G x b x   + + − − n x 1 x 1 x    Backwards Euler method t t t t + + 1 1 x x x x  Trapezoidal method     + C G b b C G     + = + + − n n x 1 x n n x x     + − − x 1 x  Coupled HSI  2  2  2  t t t t + + 1 1 x x x x

Time Domain Analysis V1 for d=0.5cm Time vs Length V2 for d=0.5cm

Conclusion  Expected delivery but need improvement  Good feedback for future optimization  Next step  CPU time complexity extraction  Complete accuracy evaluation by L2 error norm  MOR  Parallel simulation

Special Thanks  Professor Sourajeet Roy  Vibhanshu Katiyar

Sources  [1] E. Lelarasmee, A. E. Ruehli, and A. L. Sangiovanni-Vincentelli, “The waveform relaxation method for time-domain analysis of large-scale integrated circuits,” IEEE Trans. CAD Integr. Circuits Syst., vol. 1, no. 3,pp. 131–145, Jul. 1982.  [2] J. White and A. L. Sangiovanni-Vincentelli, Relaxation Techniques for the Simulation of VLSI Circuits. Norwell, MA: Kluwer, 1987.  [3] Roy, Sourajeet. “Chapter 1: Formulation of Network Equations.” 2014  [4] Roy, Sourajeet. “Chapter 3: Numerical Integration Techniques of Differential Equations.” 2014  [5] Roy, Sourajeet. “Chapter 5 High Speed Interconnects.” 2014