Hardwired Networks on Chip in FPGAs to Unify Functional and Con fi - PowerPoint PPT Presentation

Hardwired Networks on Chip in FPGAs to Unify Functional and Con fi guration Interconnects Kees Goossens 1,2 Martijn Bennebroek 3 Jae Young Hur 2 Muhammad Aqeel Wahlah 2 1 Research, NXP Semiconductors 2 Computer Engineering, Delft University of Technology 3 Philips Research

2 overview conventional FPGA – separate hard configuration interconnect and soft NOC proposed FPGA – single hard NOC for configuration, programming, data hardware architecture boot procedure performance : cost analysis conclusions configuration: loading bitstream programming: writing MMIO registers 2008-04-08 NOCS

3 conventional FPGA frame ... ... soft IP are configured in frame configurable logic blocks (CLB) configuration interconnect CLB CLBs are interconnected with switch boxes (shown as fat arrows) ... dedicated configuration interconnect to access soft IP frames (minimum unit of reconfiguration) frames and CLBs are orthogonal frame ... ... (22 frames cover 16 CLBs in Virtex4) frame hence minimum coherent unit of reconfiguration is 22 frames CLB CLB configuration IO functional IO 2008-04-08 NOCS

4 proposed FPGA CFR unified configuration and functional interconnect configuration and function region (CFR) ... – cf. Virtex4’s 22 frames – but can be orthogonal and independent ... as in current FPGAs – interconnected as in current FPGAs (see red arrows): no “tiles” CFR NOC unifies & connects to 1. functional data ports of IP 2. functional programming ports of IP (MMIO) 3. configuration ports of soft IP (bitstreams) 2008-04-08 NOCS

5 proposed FPGA soft CFR unified configuration and functional interconnect configuration and function region (CFR) IP ... – cf. Virtex4’s 22 frames – but can be orthogonal and independent ... as in current FPGAs – interconnected as in current FPGAs (see red arrows): no “tiles” soft IP NOC unifies & connects to 1. functional data ports of IP embedded memory, memory controller 2. functional programming ports of IP (MMIO) encryption / CRC 3. configuration ports of soft IP (bitstreams) decryption 1 & 2 for both soft & hard IP hard IP NOC is partially hard & soft functional IO enables conversion of data � bitstreams 2008-04-08 NOCS

6 proposed FPGA configuration data NI kernel functional & programming data CFR unified configuration and functional interconnect NI shell more details on all data types ... – soft:hard balance – mixing of configuration:functional data ... NIK on one or more NI kernels – place of boot module NIK B NI shell – possibility of bridging to soft NOC CFR soft NOC embedded memory, shown: NI memory controller – NI kernel to both config & fnal ports encryption / CRC NIK – NI kernel to conf ports only decryption – bridge to soft NOC (= NI kernel) NIK – hard NI kernel & shell for shared NIK functional IO memory IP (memories) NIK – hard kernel to streaming IPs boot configuration NI (en/decryption & IO) module IO 2008-04-08 NOCS

7 conventional IP & network interface (NI) IP NI shell NI kernel req1 req1 data port IP has data and master port port port QoS and FSM control (MMIO) ports resp1 packetisation resp1 FSM both are connected to resp2 MMIO slave resp2 L2 the NOC: prog. port port port port FSM unified data & req2 req2 IP programming interconnect L1 transactions; peer-to-peer packets; IP protocol streaming data; NOC link width data width NOC link width 2008-04-08 NOCS

8 conventional NI IP NI shell NI kernel req1 req1 data port only NIs of NOC are master port port port QoS and FSM programmed resp1 packetisation resp1 FSM using the NOC itself resp2 MMIO slave resp2 L2 prog. port unified IP & NOC port port port FSM programming req2 req2 L1 NI shell resp4 resp4 port port port FSM req4 req4 TDMA MMIO slave prog. port req4 table paths resp4 credits 2008-04-08 NOCS

9 NI in FPGA context CFR soft NI shell hard NI kernel (soft IP) req1 req1 data port NI kernel is hard master port port port QoS and FSM resp1 packetisation IP and its shell can be resp1 FSM soft or hard resp2 MMIO slave resp2 L2 prog. port hard shell for e.g.: port port port FSM processor, memory, IO req2 req2 soft IP is configured by resp3 conf. port slave port bitstream transported L1 req3 via the NOC hard NI shell resp4 resp4 unified interconnect for port port port FSM req4 – data req4 – NI & NOC programming – configuration TDMA MMIO slave prog. port req4 table paths resp4 credits 2008-04-08 NOCS

10 configuration & programming conventional configuration 1: configure module 2: 3: 4: programming NOC & IP program NOC program IP application boot functional module NOC IP functional reset all 2008-04-08 NOCS

11 configuration & programming conventional configuration 1: configure module 2: 3: 4: programming NOC & IP program NOC program IP application boot functional module NOC IP functional reset all new 1: 2: 3: 4: 5: config. mod. prog. NOC conf. IP prog. IP application boot module NOC IP functional reset functional boot module reset IP & NOC 2008-04-08 NOCS

12 configuration & programming boot hard NI shell NI kernel module 1. program the NOC req1 port port QoS and resp1 packetisation connect address FSM LUT boot module & L2 req2 (external) memories d port port containing bitstreams to resp2 configuration ports of req master port soft IP (CFR) port resp req3 L1 port port i resp4 bitstream configuration IO TDMA req req4 MMIO slave table prog. port master port port port paths resp4 credits programming connection internal history FIFO 2008-04-08 NOCS

13 configuration & programming boot hard NI shell NI kernel module 1. program the NOC req1 2. configure the soft IP port port QoS and resp1 packetisation address FSM LUT send bitstreams over the L2 req2 NOC from (external) d port port memories to CFRs resp2 req master port port resp req3 L1 port port i resp4 bitstream configuration IO TDMA req req4 MMIO slave table prog. port master port port port paths resp4 credits configuration connection programming connection internal history FIFO 2008-04-08 NOCS

14 configuration & programming boot hard NI shell NI kernel module 1. program the NOC req1 2. configure the soft IP port port QoS and resp1 packetisation 3. program the soft IP address FSM LUT L2 req2 “normal boot” of SOC d port port boot module acts as resp2 req control processor master port port reprogram NOC with resp req3 connections from L1 port port i boot module to resp4 bitstream IP MMIO configuration IO programming TDMA req req4 MMIO slave table prog. port master ports port port port paths resp resp4 program IP credits configuration connection programming connection internal history FIFO 2008-04-08 NOCS

15 configuration & programming boot hard NI shell NI kernel module 1. program the NOC req1 2. configure the soft IP port port QoS and resp1 packetisation 3. program the (soft) IP address FSM LUT 4. send data to (soft) IP L2 req2 d port port “functional mode” resp2 req master port port resp req3 L1 port port i resp4 bitstream configuration IO TDMA req req4 MMIO slave table prog. port master port port port paths resp4 credits configuration connection data connection programming connection internal history FIFO 2008-04-08 NOCS

16 configuration & programming boot hard NI shell NI kernel module 1. program the NOC req1 2. configure the soft IP port port QoS and resp1 packetisation 3. program the (soft) IP address FSM LUT 4. send data to (soft) IP L2 req2 5. use bitstreams as d port port functional data resp2 req master port port (de)compression resp req3 de/encryption L1 port port i resp4 synthesis bitstream optimisation configuration IO etc. TDMA req req4 MMIO slave table prog. port master port port port paths resp resp4 credits configuration connection data connection programming connection internal history FIFO 2008-04-08 NOCS

17 performance & cost compare – dedicated configuration interconnect & soft NOC, with – unified hard NOC on – area – functional speed – configuration footprint (bits) – configuration & programming time 2008-04-08 NOCS

18 performance & cost essentially, it all depends on – area soft:hard ≈ 35:1 – speed soft:hard ≈ 3.5:1 – configuration footprint of soft NOC (bitstream) : programming footprint of hard NOC (MMIO registers) ≈ 214:1 resulting in – boot time soft:hard ≈ 1:200 – functional performance:cost (bit/sec:area) soft:hard ≈ 1:147 2008-04-08 NOCS

19 performance & cost percentage cost of router + NI kernel against CFR size (# LUTs) 10% area cost for interconnect implies CFR of ≈ 80,000 LUTs (soft NOC) ≈ 1,400 LUTs (hard NOC) 2008-04-08 NOCS

20 performance & cost # CFRs against their size (# LUTs) # of CFRs of 1000 LUTs ≈ 19 CFRs (soft NOC) ≈ 144 CFRs (hard NOC) 2008-04-08 NOCS