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HARDWARE SPECULATION Mahdi Nazm Bojnordi Assistant Professor School of Computing University of Utah CS/ECE 6810: Computer Architecture Overview Announcement Homework 3 is due tonight (11:59PM) Midterm exam: Oct. 14 th (right after

  1. HARDWARE SPECULATION Mahdi Nazm Bojnordi Assistant Professor School of Computing University of Utah CS/ECE 6810: Computer Architecture

  2. Overview ¨ Announcement ¤ Homework 3 is due tonight (11:59PM) ¤ Midterm exam: Oct. 14 th (right after Fall break) ¨ This lecture ¤ Out-of-order pipeline n Issue queue n Register renaming n Branch recovery n Speculated execution

  3. Recall: Out-of-Order Execution ¨ Producer-consumer chains on the fly ¤ Register renaming: remove anti-/output-dependences via register tags ¤ Limited by the number of instructions in the instruction window (ROB) ¨ Out-of-order issue (dispatch) ¤ Broadcast tags to waiting instructions ¤ Wake up ready instructions and select among them ¨ Out-of-order execute/complete ¨ In-order fetch/decode and commit

  4. Out-of-Order Pipelines ¨ Distributed reservation stations ¤ In-order issue/dispatch Res. Station FU-1 … Register Res. Station FU-n File Inst. Inst. Res. Station Branch Memory Decoder Res. Station Data Memory Re-Order Buffer (ROB) Fetch Decode Rename Issue Execute Complete Commit

  5. Out-of-Order Pipelines ¨ Out of order issue/dispatch to functional units ¤ Out-of-order issue/dispatch Issue Queue (IQ) FU-1 … Register FU-n File Inst. Inst. Branch Memory Decoder Data Memory Re-Order Buffer (ROB) Fetch Decode Rename Issue Execute Complete Commit

  6. Out-of-Order Issue Queue ¨ Two step wakeup and select logic broadcast tag Rdy-1 Reg-1 Reg-2 Rdy-2 … = =

  7. Out-of-Order Issue Queue ¨ Two step wakeup and select logic broadcast tag Rdy-1 Reg-1 Reg-2 Rdy-2 … = = … Rdy-1 Reg-1 Reg-2 Rdy-2 … = =

  8. Out-of-Order Issue Queue ¨ Two step wakeup and select logic broadcast tag Selection Logic Rdy-1 Reg-1 Reg-2 Rdy-2 … = = Selected Instructions … Rdy-1 Reg-1 Reg-2 Rdy-2 … = =

  9. Register Renaming ¨ Register aliasing table for fast lookup Issue Queue (IQ) Register FU-1 Aliasing … Table Register FU-n (RAT) File Inst. Inst. Branch Memory Decoder Data Memory Re-Order Buffer (ROB) Fetch Decode Rename Issue Execute Complete Commit

  10. Register Renaming ¨ Register aliasing table for fast lookup Issue Queue (IQ) Register FU-1 Aliasing … Table Register FU-n (RAT) File Inst. Inst. Branch Memory Decoder Where Data Memory to write? Re-Order Buffer (ROB) Fetch Decode Rename Issue Execute Complete Commit

  11. Register Renaming ¨ Register aliasing table for fast lookup How to add entries Issue Queue (IQ) to RAT? Register FU-1 Aliasing … Table Register FU-n (RAT) File Inst. Inst. Branch Memory Decoder Where Data Memory to write? Re-Order Buffer (ROB) Fetch Decode Rename Issue Execute Complete Commit

  12. Register Renaming ¨ Register aliasing table for fast lookup How to add entries Issue Queue (IQ) to RAT? Search the table for Register FU-1 Aliasing an unallocated tag! … Table Register FU-n (RAT) File Inst. Inst. Branch Memory Decoder Where Data Memory to write? Re-Order Buffer (ROB) Fetch Decode Rename Issue Execute Complete Commit

  13. Register Renaming ¨ Free register list for fast register renaming Issue Queue (IQ) Register FU-1 Aliasing … Table Register FU-n (RAT) File Inst. Inst. Free Branch Memory Decoder Register List Data Memory Re-Order Buffer (ROB) Fetch Decode Rename Issue Execute Complete Commit

  14. Register Renaming ¨ Free register list for fast register renaming Proceed only if there is free space in IQ, Issue Queue (IQ) ROB, and Free List Register FU-1 Aliasing … Table Register FU-n (RAT) File Inst. Inst. Free Branch Memory Decoder Register List Data Memory Re-Order Buffer (ROB) Fetch Decode Rename Issue Execute Complete Commit

  15. Register Renaming ¨ Free register list for fast register renaming Proceed only if there is free space in IQ, Issue Queue (IQ) ROB, and Free List Register FU-1 When is it safe to Aliasing … free a tag? Table Register FU-n (RAT) File Inst. Inst. Free Branch Memory Decoder Register List Data Memory Re-Order Buffer (ROB) Fetch Decode Rename Issue Execute Complete Commit

  16. Example: Instruction Commit ¨ Update value in ROB R1->T0 T0=V2+V3 R10->T1 R1: ?? R2: V2 R3: V3 … T2, T3, T4, … T1=Mem[10] Head … ld,R10 +, R1 T4 T3 T2 T1 T0

  17. Example: Instruction Commit ¨ Update value in ROB T0,V1 R1->T0 T0=V2+V3 R10->T1 R1: ?? R2: V2 R3: V3 … T2, T3, T4, … T1=Mem[10] … ld,R10 +, R1 T4 T3 T2 T1 T0

  18. Example: Instruction Commit ¨ Register file write R1->T0 ALU R10->T1 R1: ?? R2: V2 R3: V3 … T2, T3, T4, … T1=Mem[10] R1,V1 … ld,R10 +, R1 T4 T3 T2 T1 T0

  19. Example: Instruction Commit ¨ Update tables and ROB R10->T1 ALU R1: V1 R2: V2 R3: V3 … T2, T3, T4, …, T0 T1=Mem[10] … ld,R10 T4 T3 T2 T1 T0

  20. Example: Instruction Rename ¨ Allocate entries on ROB, IQ, and FL R10->T1 ALU R1: V1 R2: V2 R3: V3 R2=R1+R2 … T2, T3, R3=R1+R2 T4, …, R5=R1+R9 T0 T1=Mem[10] … ld,R10 T4 T3 T2 T1 T0

  21. Example: Instruction Rename ¨ Allocate entries on ROB, IQ, and FL T2=V1+V2 R10->T1 ALU R2->T2 R1: V1 R2: ?? R3: V3 R3=R1+R2 … R5=R1+R9 T3, T4, …, T0 T1=Mem[10] … +,R2 ld,R10 T4 T3 T2 T1 T0

  22. Example: Instruction Rename ¨ Allocate entries on ROB, IQ, and FL T3=V1+T2 T2=V1+V2 R10->T1 ALU R2->T2 R1: V1 R3->T3 R2: ?? R3: ?? R5=R1+R9 … T4, …, T0 T1=Mem[10] … +,R3 +,R2 ld,R10 T4 T3 T2 T1 T0

  23. Example: Instruction Rename ¨ Instruction has to wait for free resources T3=V1+T2 T2=V1+V2 R10->T1 ALU R2->T2 R1: V1 R3->T3 R2: ?? R3: ?? R5=R1+R9 … T4, …, T0 T1=Mem[10] … +,R3 +,R2 ld,R10 T4 T3 T2 T1 T0

  24. Example: Instruction Issue ¨ Issue ready instruction if free FU exists T3=V1+T2 R10->T1 T2=V1+V2 R2->T2 R1: V1 R3->T3 R2: ?? R3: ?? R5=R1+R9 … T4, …, T0 T1=Mem[10] … +,R3 +,R2 ld,R10 T4 T3 T2 T1 T0

  25. Example: Instruction Issue ¨ Out-of-order issue is now possible T3=V1+T2 T4=V1+V9 R10->T1 T2=V1+V2 R2->T2 R1: V1 R3->T3 R2: ?? R5->T4 R3: ?? … T5, …, T0 T1=Mem[10] … +,R5 +,R3 +,R2 ld,R10 T4 T3 T2 T1 T0

  26. Example: Instruction Issue ¨ Out-of-order issue is now possible T3=V1+T2 T4=V1+V9 R10->T1 T2=V1+V2 R2->T2 R1: V1 R3->T3 R2: ?? R5->T4 R3: ?? … T5, …, T0 T1=Mem[10] … +,R5 +,R3 +,R2 ld,R10 T4 T3 T2 T1 T0

  27. Example: Instruction Issue ¨ Out-of-order issue is now possible T3=V1+T2 T4=V1+V9 T2,V2 R10->T1 T2=V1+V2 R2->T2 R1: V1 R3->T3 R2: ?? R5->T4 R3: ?? … T5, …, T0 T1=Mem[10] … +,R5 +,R3 +,R2 ld,R10 T4 T3 T2 T1 T0

  28. Example: Instruction Issue ¨ Wakeup and select T3=V1+V2 T4=V1+V9 R10->T1 ALU R2->T2 R1: V1 R3->T3 R2: ?? R5->T4 R3: ?? … T5, …, T0 T1=Mem[10] … +,R5 +,R3 +,R2 ld,R10 T4 T3 T2 T1 T0

  29. Example: Instruction Issue ¨ Keep the program order to avoid starvation T4=V1+V9 R10->T1 T3=V1+V2 R2->T2 R1: V1 R3->T3 R2: ?? R5->T4 R3: ?? … T5, …, T0 T1=Mem[10] … +,R5 +,R3 +,R2 ld,R10 T4 T3 T2 T1 T0

  30. Example: Instruction Issue ¨ Keep the program order to avoid starvation T4=V1+V9 T3,V3 R10->T1 T3=V1+V2 R2->T2 R1: V1 R3->T3 R2: ?? R5->T4 R3: ?? … T5, …, T0 T1=Mem[10] … +,R5 +,R3 +,R2 ld,R10 T4 T3 T2 T1 T0

  31. Example: Instruction Execute ¨ Issue ready instructions R10->T1 T4=V1+V9 R2->T2 R1: V1 R3->T3 R2: ?? R5->T4 R3: ?? … T5, …, T0 T1=Mem[10] … +,R5 +,R3 +,R2 ld,R10 T4 T3 T2 T1 T0

  32. Example: Instruction Execute ¨ Issue ready instructions T4,V4 R10->T1 T4=V1+V9 R2->T2 R1: V1 R3->T3 R2: ?? R5->T4 R3: ?? … T5, …, T0 T1=Mem[10] … +,R5 +,R3 +,R2 ld,R10 T4 T3 T2 T1 T0

  33. Example: Instruction Execute ¨ Update ROB R10->T1 ALU R2->T2 R1: V1 R3->T3 R2: ?? R5->T4 R3: ?? … T5, …, T0 T1=Mem[10] … +,R5 +,R3 +,R2 ld,R10 T4 T3 T2 T1 T0

  34. Example: Instruction Execute ¨ Update ROB R10->T1 ALU R2->T2 R1: V1 R3->T3 R2: ?? R5->T4 R3: ?? … T5, …, T0 T1,V10 T1=Mem[10] … +,R5 +,R3 +,R2 ld,R10 T4 T3 T2 T1 T0

  35. Register Renaming Example ¨ Where values are stored? Issue Queue Functional Units Register File Decode Queue R1 R1 ß R1 + R2 tags R2 R2 ß R1 - R3 R1 Reorder Buffer R3 BEQ R2, R0 R2 … ROB 1 T0 R3 ß R1 ^ R2 R3 ROB 2 T1 R1 ß R3 & R2 … ROB 3 T2 ROB 4 T3 ROB 5 T4

  36. Register Renaming Example ¨ Where values are stored? Issue Queue Functional Units T0 ß R1 + R2 Register File Decode Queue R1 R1 ß R1 + R2 tags R2 R2 ß R1 - R3 R1 T0 Reorder Buffer R3 BEQ R2, R0 R2 … R1 ROB 1 T0 R3 ß R1 ^ R2 R3 ROB 2 T1 R1 ß R3 & R2 … ROB 3 T2 ROB 4 T3 ROB 5 T4

  37. Register Renaming Example ¨ Where values are stored? Issue Queue Functional Units T0 ß R1 + R2 T1 ß T0 - R3 Register File Decode Queue R1 R1 ß R1 + R2 tags R2 R2 ß R1 - R3 R1 T0 Reorder Buffer R3 BEQ R2, R0 R2 T1 … R1 ROB 1 T0 R3 ß R1 ^ R2 R3 ROB 2 T1 R2 R1 ß R3 & R2 … ROB 3 T2 ROB 4 T3 ROB 5 T4

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