Hardware Implementation of Droop Control for Isolated AC Microgrid - PowerPoint PPT Presentation

Hardware Implementation of Droop Control for Isolated AC Microgrid By: Cristina Guzman Alben Cardenas Kodjo Agbossou Université du Québec à Trois-Rivières Québec-Canada

Outline Introduction Droops control principle ADALINE estimation technique Hardware implementation of ADALINE and Droops control Co-simulation results Experimental results Conclusion 2

Introduction Smart Grid: Integration of DER privileging Renewable energy using Voltage Source Inverters (VSI) Alternative and distributed energy Power electronics source interfaces G WG VSI VSI Energy storage system DC Link H O Fuel cell H2 VSI Electrolyser 3

Introduction Literature propositions made around the stability of the isolated microgrids. PCC Distortion Interfaces de Line puissance currents Techniques based on impedances Communication control VSI Local control VSI Techniques Combined Local control with communication VSI 4

Droops control principle Basic representation of VSI power sharing 2 V V V 1 2 P cos cos( ) Z Z X P * 2 V V V w w m P P * 1 2 Q sin sin( ) V 1 V Z Z 2 S P jQ V V 1 2 X Q P sin Z V V * 1 2 V V n Q Q * V 2 V V V 1 1 2 Q cos Z Z 5

Droops control principle Basic representation of VSI power sharing w * * V * V V n Q Q * w w m P P m n Δw w 0 ΔV V 0 – Q max P max Q 0 Q max 0 P 0 P 0 Q (W) (var) 6

ADALINE estimation technique Fourier decomposition X pattern vector Weight vector W V ( t ) A [ A cos( n t ) B sin( n t )] PCC 0 n n n 1 sin( t ) B 1 Estimated signal cos( t ) A 1  ˆ X  T W y ( k ) W ( k ) X ( k ) sin( N t ) B N cos( N t ) A N Estimation error _ W ( k 1 ) W ( k ) e ( k ) X ( k ) ˆ Measured e ( k ) y ( k ) y ( k ) + N signal Widrow-Hoff learning rule y(k) ADALINE :Adaptive Neural Network 7

Hardware implementation of Droops and ADALINE control V LD Conventional V/f Droops and ADALINE based voltage control V DC V mes IGBT VSI Droops Control Frequency Droop w/P I mes w ref V mes f droop VF DDS + Mn Sine wave - generator S&H x I 0 I 1 Voltage Droop V/Q P P&Q V ref ADALINE V 0 V droop Nn Q + calculus V 1 - x V_ LD V _REF_Droops Voltage Control k PWM V_ REF_mod V mes i k p s VSI 8 8

Hardware implementation of Droops and ADALINE control Simulink functional blocks diagram of the conventional Droops Continuous powergui 120 *pi In E1_W_REF Wref System z -1 Delay 14 Generator a a<b cast a z -1 P_estime cast In18f7 a>b b sel cast z -1 a Out_18f 7 Convert 3 Relational 2 b z -1 Convert 5 sel dW h1ms a - b a Convert 2 z -1 d0 b z -3 Relational 1 (ab) FILTRE _8MS3 a z -3 AddSub 1 b z -1 z -1 z -1 (ab) d0 b d1 System generator Mult 2 Delay Delay 3 z -1 0.0038 /2 1 In Mult d1 Sat 2 Gain 3 E3_M Delay 12 M Sat1 functional blocks 7.539794921875 0.159149169921875 -7.539794921875 Constant Constant 8 Constant 1 diagram of the 115*sqrt(2) In E2_V_REF Vref z -1 a Delay 13 a conventional Droops a<b a>b cast z -1 cast z -1 sel b sel Q_estime cast In18f7 b Convert 1 a Convert Out_18f 7 Relational 4 z -1 Relational 3 a - b Convert 4 h1ms control z -1 z -1 z -1 d0 d0 b a z -1 FILTRE _8MS2 z -3 Qmes (ab) Delay 2 AddSub b Delay 1 d1 d1 Mult 1 Sat3 Sat4 z -1 0.0326 /2 In 1 E4_N Delay 11 Gain N 8.4852294921875 -8.4852294921875 Constant 2 Constant 3 9 9

Hardware implementation of Droops and ADALINE control Real scenario /Simulation and experimental VSI characteristics Description (units) VSI 1 VSI 2 Switching frequency (kHz) 12 12 IGBT max. current and voltage (A) (V) 16, 600 16, 600   Filter inductor (mH) 17 12   Filter capacitor (µF) 3 1   Resistive line value (m Ω ) 21.8 38.6   Inductive line value (µH) 90 170   Coefficient m value 3.9035e-4 2.5466e-4   Coefficient n value 0.0066 0.0047 The inverters characteristics are similar but not identical; the inverters output filters local synchronization and control of inverters; different line impedances between VSI output and PCC; m and n are calculated as a function of the VSI powers. 10

Experimental set-up system PC Windows One VSI system Matlab/Simulink /Xilinx User Interface USB-JTAG Link Measurement board (ADC and isolation circuits) Xilinx FPGA XUP V2P Board xc2vp30-7ff896 Current and voltage LEM Sensors VSI control LEM-LV25 LEM-LAH-50P and protection signals Output filter LOAD 195V DC source 11

Hardware implementation of Droops and ADALINE control Two VSI system Test bench Line emulators Line emulators VSI 2 VSI 1 195V DC source 195 V DC source FPGA FPGA measurement measurement control control 12

Co-simulation results Two converters evaluation 61 5 Droop Inv1 Inverter 1 Estimated Inv1 Frequency (Hz) 60.5 Droop Inv2 Inverter 2 Current (A) Estimated Inv2 60 0 59.5 59 -5 0 0.1 0.2 0.3 0.4 0.5 0.6 0 0.1 0.2 0.3 0.4 0.5 0.6 Time(s) Time(s) Synchronization 170 200 Inverter 1 imposes of VSI is 100 165 Inverter 2 Voltage (V) Voltage (V) made automatically 0 160 -100 155 -200 150 0 0.1 0.2 0.3 0.4 0.5 0.6 0 0.1 0.2 0.3 0.4 0.5 0.6 Time(s) Time(s) Negligible effects The output voltage on voltage THD is not affected Good power sharing 13 Simulating the same characteristics physiques

Experimental results Test 1: one VSI experimental validation 200 150 Active V droop Puissance (W)/ (VAR) 150 Reactive Vc estimated 145 Peak Voltage 100 140 50 135 0 Voltage 130 -50 58 58.5 59 59.5 60 60.5 61 61.5 62 58 58.5 59 59.5 60 60.5 Load variations 61 61.5 62 Time (s) estimation is well Time (s) achieved Droop 60.2 Estimated frequency Estimated 60.1 60 59.9 59.8 Frequency inside 59.7 the permitted 59.6 58 58.5 59 59.5 60 60.5 61 61.5 62 Time (s) limits 14 Verification of the correct operation of the implemented droop/ADALINE control.

Experimental results Test 2: Two parallel VSI experimental results t2 t3 t4 t5 t1 VSI 2 Power VSI 1 15

Experimental results Test 2: Two parallel VSI experimental results t2 t3 t4 t5 t1 VSI 2 Frequency VSI 1 16

Experimental results Test 2: Two parallel VSI experimental results t2 t3 t4 t5 t1 VSI 2 Voltage VSI 1 17

Experimental results Implementation cost of control algorithms for the Xilinx xc2vp30-7ff896 FPGA Resource Used Available % Usage Slices 7,122 13,696 52% 4 input LUTs 11,698 27,392 42% RAMB16s 66 136 48% MULT18X18s 76 136 55% FPGA Slices Used Available 18

Conclusion Real view of the Droops control / VF-ADALINE network for VSI synchronization and load sharing in a microgrid. The FPGA implementation has permitted a real- time control and power analysis without communication between VSIs Good steady and transient response using ADALINE based control. Current and future works: advanced local control strategies going forward future smart microgrids. 19

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Anexe Experimental setup parameters: AC Power Source: 120VAC/60Hz. Signals sampling period: T s =10µs. FPGA clock period: T FPGA =10ns. Fundamental frequency: f 0 =60Hz ROM sine table length: 2P=215 Power electronics converter characteristics: Voltage Source Inverters: 16A, 600V IGBT full bridge (IRAMX16UP60A) DC source voltage: 195V.