Guess What? Caching! Translation-Lookaside Buffer (TLB) stores for - PowerPoint PPT Presentation

Guess What? Caching! Translation-Lookaside Buffer (TLB) stores for future use a successful translation between a Speeding Up Virtual Page Number (VPN) and a Physical Frame Number (PFN) Address Translation on a TLB hit, translation is achieved without accessing PT on a TLB miss Page Table is accessed if VA is invalid, exception (segmentation fault) if VA is valid, but page is not present, load page (we’ll talk about it soon) if VA is valid and page is present, update TLB and retry op Why Does it Work? So Sorry I Missed You Spatial locality TLB Misses can be handled in Hardware program is likely to access memory locations close to HW updates TLB and retries instruction each other in VA space HW uses PTBR to find Page Table (PT) only first access to a page causes a TLB miss and Page HW performs full address translation Table access TLB misses can be handled in Software Temporal locality TLB miss causes a trap program is likely to quickly access again the same HW raises an exception, moves to kernel mode, and memory locations jumps to trap handler if new access happens while translation still in TLB, mo need to access Page Table Handler goes through PT and updates TLB better not trigger a TLB miss while running the handler! HW returns from serving the miss with PC pointing to the instruction that caused the trap, so it is re-executed

Speeding things up: Virtually Addressed Caches The TLB Contents of Physical Memory indexed by VA Virtual Virtual Virtual Address Address Address Virtual Page p o CPU CPU TLB Miss Miss Invalid Exception Cache Table VPN PFN Access Hit Hit Valid & Present TLB hit Physical Data PFN PFN f addresses o Offset Physical + TLB Memory Physical Address TLB miss Data p Data EAT: (1+ � ) α +(2+ � )(1 − α ) f c PTBR i ( : hit ratio) f c m = 2+ � − α e e e α c s t s 81 82 i v Page Table Base Register e Physically TLB Consistency - I Addressed Caches On context switch Virtual Virtual Address Address VA Virtual Page CPU TLB Miss Miss Invalid Exception Cache Table VAs of old process should no longer be valid Hit Hit Change PTBR — but what about the TLB? Valid & Present Data PFN PFN PA Offset Physical Physical + Miss Cache Memory Physical Address Hit Data Data Data 83 84

TLB Consistency - I TLB Consistency - II On context switch What if OS changes permissions on a page? VAs of old process should no longer be valid What if permissions are reduced? Change PTBR — but what about the TLB? OS must purge affected TLB entries (e.g., on copy-on-write) Option 1: Flush the TLB What if permissions are expanded? Option 2: Add pid tag to each TLB entry either cause hardware to load new entries PID VPN PFN Access 1 0x0053 0x0012 R/W TLB Entry or cause an exception, so handler can update TLB entry as necessary Ignore entries with wrong PIDs 85 86 What if we miss A different approach in the TLB? Suppose a 64-bit VAS, with 4KB page and a What if mapping size were proportional to 512MB physical memory the number of frames, instead of pages? Page table has 2 52 entries If PTE = 16 bytes, Page table size = 2MB At 4 bytes/PTE, Page Table is 16 Petabytes! And since all processes share the same physical frames, just one global page table! per process! For Page Table at each level to fit in a single Inverted page tables page, each level should span at most 10 bits 6 levels of paging!! But frames are few… only 2 29 /2 12 = 128K 87 88

Basic Inverted Page Registers Page Table Architecture (a.k.a. Inverted Page Tables) For each frame, a register containing Residence bit is the frame occupied? Page number of the occupying page CPU pid p offset PFN offset Id of the process currently mapping the frame Physical VAS of different processes may map the Memory same page number to different frames! 0 1 Protection bits search Searched by page number PFN - 1 PFN pid p 89 Inverted Page Table 90 Where have all the Hashed Inverted pages gone? Page Tables Hash Anchor Table maps <pid, VPN> to an entry Searching 128KB of registers on every of the Inverted Page Table memory reference is not fun Collisions handled by chaining If the number of frames is small, the page registers can be placed in an associative pid VPN Offset PFN pid VPN next 0 0x1 0x123 memory — but… 0x0 1 0xa63 0x184fa 1 1 3 4 0x184fc Large associative memories are expensive hash 0x184fa 0 0x1 ---- 3 0x31ab 0x0a921 hard to access in a single cycle 0x184fb 2 0xaf013 Inverted 0x0 consume lots of power Page Table 5 Hash Anchor Table (typically, #buckets Physical Memory Address 0x184fa 0x123 equals #frames) 91 92