Graphics Processing Unit (GPU) Devices Edward J. Wyrwas - PowerPoint PPT Presentation

Graphics Processing Unit (GPU) Devices Edward J. Wyrwas edward.j.wyrwas@nasa.gov 301-286-5213 Lentech, Inc. in support of NEPP Acknowledgment: This work was sponsored by: NASA Electronic Parts and Packaging (NEPP) 1 P resented by Edward J. Wyrwas at the 2018 NEPP Electronics Technology Workshop (ETW), NASA GSFC, Greenbelt, MD, June 18-21, 2018.

Acronyms Acronym Definition Acronym Definition Acronym Definition 1MB 1 Megabit Gov't Government NRL Naval Research Laboratory 3D Three Dimensional GPU Graphics Processing Unit NRO United States Navy National Reconnaissance Office 3DIC Three Dimensional Integrated Circuits GRC NASA Glenn Research Center NSWC Crane Naval Surface Warfare Center, Crane Division ACE Absolute Contacting Encoder GSFC Goddard Space Flight Center OCM On-chip RAM ADC Analog to Digital Converter GSN Goal Structured Notation PBGA Plastic Ball Grid Array AEC Automotive Electronics Council GTH/GTY Transceiver Type PC Personal Computer AES Advanced Encryption Standard HALT Highly Accelerated Life Test PCB Printed Circuit Board AF Air Force HAST Highly Accelerated Stress Test PCIe Peripheral Component Interconnect Express AFRL Air Force Research Laboratory HBM High Bandwidth Memory PCIe Gen2 Peripheral Component Interconnect Express Generation 2 AFSMC Air Force Space and Missile Systems Center HDIO High Density Digital Input/Output AMS Agile Mixed Signal HDR High-Dynamic-Range PLL Phase Locked Loop ARM ARM Holdings Public Limited Company HiREV High Reliability Virtual Electronics Center POL point of load BGA Ball Grid Array HMC Hybrid Memory Cube PoP Package on Package BOK Body of Knowledge HP Labs Hewlett-Packard Laboratories PPAP Production Part Approval Process CAN Controller Area Network HPIO High Performance Input/Output Proc. Processing CBRAM Conductive Bridging Random Access Memory HPS High Pressure Sodium PS-GTR High Speed Bus Interface CCI Correct Coding Initiative HUPTI Hampton University Proton Therapy Institute QDR quad data rate CGA Column Grid Array I/F interface QFN Quad Flat Pack No Lead CMOS Complementary Metal Oxide Semiconductor I/O input/output QSPI Serial Quad Input/Output Xilinx ceramic flip-chip (CF and CN) packages are ceramic column I2C Inter-Integrated Circuit R&D Research and Development CN grid array (CCGA) packages i2MOS Microsemi second generation of Rad-Hard MOSFET R&M Reliability and Maintainability COTS Commercial Off The Shelf IC Integrated Circuit RAM Random Access Memory CRC Cyclic Redundancy Check IC Integrated Circuit ReRAM Resistive Random Access Memory CRÈME Cosmic Ray Effects on Micro Electronics I-Cache independent cache RGB Red, Green, and Blue CRÈME MC Cosmic Ray Effects on Micro Electronics Monte Carlo IUCF Indiana University Cyclotron Facility RH Radiation Hardened CSE Crypto Security Engin JFAC Joint Federated Assurance Center SATA Serial Advanced Technology Attachment CU Control Unit JPEG Joint Photographic Experts Group SCU Secondary Control Unit D-Cache defered cache Joint Test Action Group (FPGAs use JTAG to provide SD Secure Digital JTAG DCU Distributed Control Unit access to their programming debug/emulation functions) SD/eMMC Secure Digital embedded MultiMediaCard DDR Double Data Rate (DDR3 = Generation 3; DDR4 = Generation 4) SD-HC Secure Digital High Capacity KB Kilobyte SDM Spatial-Division-Multiplexing DLA Defense Logistics Agency L2 Cache independent caches organized as a hierarchy (L1, L2, etc.) SEE Single Event Effect DMA Direct Memory Access LANL Los Alamos National Laboratories SESI secondary electrospray ionization DMEA Defense MicroElectronics Activity LANSCE Los Alamos Neutron Science Center Si Silicon DoD Department of Defense LLUMC Loma Linda University Medical Center SiC Silicon Carbide DOE Department of Energy L-mem Long-Memory DSP Digital Signal Processing SK Hynix SK Hynix Semiconductor Company LP Low Power SLU Saint Louis University dSPI Dynamic Signal Processing Instrument LVDS Low-Voltage Differential Signaling Dual Ch. Dual Channel SMDs Selected Item Descriptions LW HPS Lightwatt High Pressure Sodium ECC Error-Correcting Code SMMU System Memory Management Unit M/L BIST Memory/Logic Built-In Self-Test EEE Electrical, Electronic, and Electromechanical SNL Sandia National Laboratories MBMA Model-Based Missions Assurance EMAC Equipment Monitor And Control SOA Safe Operating Area MGH Massachusetts General Hospital EMIB Multi-die Interconnect Bridge SOC Systems on a Chip Mil/Aero Military/Aerospace ESA European Space Agency SPI Serial Peripheral Interface MIPI Mobile Industry Processor Interface eTimers Event Timers STT Spin Transfer Torque MMC MultiMediaCard ETW Electronics Technology Workshop TBD To Be Determined MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor FCCU Fluidized Catalytic Cracking Unit Temp Temperature MP Microprocessor FeRAM Ferroelectric Random Access Memory THD+N Total Harmonic Distortion Plus Noise MP Multiport Fin Field Effect Transistor (the conducting channel is wrapped by a TRIUMF Tri-University Meson Facility FinFET MPFE Multiport Front-End thin silicon "fin") T-Sensor Temperature-Sensor MPU Microprocessor Unit FPGA Field Programmable Gate Array TSMC Taiwan Semiconductor Manufacturing Company Msg message FPU Floating Point Unit U MD University of Maryland NAND Negated AND or NOT AND FY Fiscal Year UART Universal Asynchronous Receiver/Transmitter NASA National Aeronautics and Space Administration GaN Gallium Nitride UFHPTI University of Florida Proton Health Therapy Institute NASA STMD NASA's Space Technology Mission Directorate GAN GIT Panasonic GaN GIT Eng Prototype Sample Ultra Random Access Memory UltraRAM Navy Crane Naval Surface Warfare Center, Crane, Indiana GAN SIT Gallium Nitride GIT Eng Prototype Sample USB Universal Serial Bus NEPP NASA Electronic Parts and Packaging Gb Gigabyte VNAND Vertical NAND NGSP Next Generation Space Processor GCR Galactic Cosmic Ray WDT Watchdog Timer NOR Not OR logic gate GIC Global Industry Classification 2 P resented by Edward J. Wyrwas at the 2018 NEPP Electronics Technology Workshop (ETW), NASA GSFC, Greenbelt, MD, June 18-21, 2018.

Outline • What the technology is (and isn’t) • Our tasks and their purpose • Roadmap • Partners • Test Readiness • Comments P resented by Edward J. Wyrwas at the 2018 NEPP Electronics Technology Workshop (ETW), NASA GSFC, Greenbelt, MD, June 18-21, 2018. 3

Technology • Graphics Processing Units (GPU) & General Purpose Graphics Processing Units (GPGPU) – Are considered a compute device or coprocessor – Is not a standalone multiprocessor (even when contained in an SoC) • Application workflow: – Run the sequential part of their workload on the CPU – which is optimized for single-threaded performance – Accelerate parallel processing using multi-thread performance on the GPU P resented by Edward J. Wyrwas at the 2018 NEPP Electronics Technology Workshop (ETW), NASA GSFC, Greenbelt, MD, June 18-21, 2018. 4

Device Packaging Nvidia TX1 SoC Intel Skylake Processor Qualcomm Adreno Nvidia GTX 1050 GPU AMD RX460 GPU P resented by Edward J. Wyrwas at the 2018 NEPP Electronics Technology Workshop (ETW), NASA GSFC, Greenbelt, MD, June 18-21, 2018. 5

Purpose • GPUs are best used for single instruction- multiple data (SIMD) parallelism – Perfect for breaking apart a large data set into smaller pieces and processing those pieces in parallel • Key computation pieces of mission applications can be computed using this technique – Sensor and science instrument input – Object tracking and obstacle identification – Algorithm convergence (neural network) – Image processing – Data compression algorithms P resented by Edward J. Wyrwas at the 2018 NEPP Electronics Technology Workshop (ETW), NASA GSFC, Greenbelt, MD, June 18-21, 2018. 6

FY18-19: GPU Testing Description: FY18-19 Plans: – Continue development of universal test suite which includes math, – This is a task over all device topologies and process output buffer (colors), memory hierarchy and neural networks – The intent is to determine inherent radiation tolerance and – Probable test structures for SEE: sensitivities – Identify challenges for future radiation hardening efforts – Nvidia (16, 14, 10nm) – Investigate new failure modes and effects – AMD (14, 10nm) – Intel (14) – Testing includes total dose, single event (proton) and reliability. – Qualcomm (10nm) Test vehicles will include a GPU devices from nVidia and other vendors as available – Compare to previous generations – Tests: – Investigate failure modes/compensation for increased – characterization pre, during and post-rad power consumption Deliverables: Schedule: – Test reports and quarterly reports FY18 Microelectronics FY19 – Expected submissions for publications T&E M J J A S O N D J F M A On-going discussions for test samples GPU Test Development NASA and Non-NASA Organizations/Procurements: SEE Testing Analysis and Comparison – Source procurements: Proton (MGH), TID (GSFC), Laser (NRL) Lead Center/PI: GSFC/Lentech/Wyrwas Co-Is: Carl Szabo P resented by Edward J. Wyrwas at the 2018 NEPP Electronics Technology Workshop (ETW), NASA GSFC, Greenbelt, MD, June 18-21, 2018. 7