George Chen Amit Dhuria Intel Cadence The TAU 2017 Contest Path - PowerPoint PPT Presentation

George Chen Amit Dhuria Intel Cadence

The TAU 2017 Contest Path Reporting Contest George Xi Amit Chen Chen Dhuria Intel Synopsys Cadence [Speaker] Sponsors: Programmable Solutions Group 2

Why Path Reporting? Path reporting occupies a large portion of static timing analysis  Core timing analysis is generated only once.  But timing report generation occurs many times, after initial timing update.  1000s+ commands may be issued for specific subset of paths to check for timing closure  Web-based dashboard systems built to parse data depend upon the path reporting infrastructure Raise awareness of the need for efficient parallelization of path reporting  Accurate handling of from/through/to parameters  Explore limitations to the performance of path reporting. Programmable Solutions Group 3

Contest Overview Leveraged past TAU Timing Contest Infrastructure Provided to Contestants Evaluation Detailed Documentation Benchmarks ~100K individual path queries across two designs Design Early and Late Design Connectivity Libraries Parasitics ( .ops ) STA Run ( .output ) Verilog ( .v ) Liberty ( .lib ) SPEF ( .spef ) Timing and path reporting tutorials, file formats, timing wrapper file ( .tau2018 ) model basics, evaluation rules, etc. Open Source Code and Binaries 1. PATMOS 2011 : NTU-Timer 5. TAU 2015 binary : Golden Memory 2. TAU 2013 : IITiMer iTimerC v2.0 Runtime 3. TAU 2014 : UI-Timer 6. OpenTimer Result* Usage 4. ISPD 2013 : .spef/.lib parsers (UI-Timer v2.0) Accuracy Performance Previous contest winners, utilities Very limited time frame: 2 months only (12/17/2017 to 2/16/2018) Contest scope: Graph-Based Analysis only, with support of • -from/-rise_from/-fall_from • -through/-rise_through/-fall_through • -to/-rise_to/fall_to Programmable Solutions Group 4

Benchmarks Based on TAU 2015 Benchmarks Design Gates Nets vga_lcd 139.5K 139.6K leon3mp_iccad 1247.7K 1248.0K Test setup  ~50K paths per testcase pre-generated by commercial timer  Used special constant-delay Liberty models to reduce/eliminate delay calculation impact. Programmable Solutions Group 5

Evaluation Metrics Overview Metric Weight Remarks Accuracy 30% Correct sub-path reported Runtime 30% Elapsed time (not user time) Memory 20% Peak memory usage, including allocated memory Documentation 20% Clear description of algorithm and features Detailed Scoring Algorithm (10 points possible) # 𝑑𝑝𝑠𝑠𝑓𝑑𝑢 𝑞𝑏𝑢ℎ𝑡  Accuracy = 3 * # 𝑢𝑝𝑢𝑏𝑚 𝑞𝑏𝑢ℎ𝑡 (custom script) min(𝑏𝑚𝑚 𝑓𝑜𝑢𝑠𝑗𝑓𝑡) 𝑓𝑜𝑢𝑠𝑧 ′ 𝑡 𝑠𝑣𝑜𝑢𝑗𝑛𝑓 (measured wall clock time using “time” cmd)  Runtime = 3 * min ( 𝑏𝑚𝑚 𝑓𝑜𝑢𝑠𝑗𝑓𝑡 )  Memory = 2 * 𝑓𝑜𝑢𝑠𝑧 ′ 𝑡 𝑛𝑓𝑛𝑝𝑠𝑧 (measured peak memory using “time” cmd) Programmable Solutions Group 6

TAU 2018 Contestants University Team National Chiao Tung University / iTimerP National Taiwan University Texas A&M University Concha-STA National Tsing Hua University BattleCats Programmable Solutions Group 7

Pei-Yu Lee 1 , Hsien-Han Cheng 1 ,Iris Hui-Ru Jiang 12 1 National Chiao Tung University 2 National Taiwan University 8

Tau2018 Contest Team Name: iTimerP Pei-Yu Lee 1 , Hsien-Han Cheng 1 ,Iris Hui-Ru Jiang 12 1 National Chiao Tung University 2 National Taiwan University

Outline  Algorithm flow  Motivation  Timing graph marking  Path searching  Experimental result 10

Algorithm Flow Initial Timing Graph Construction Block-Based Timing Analysis Forward Propagating Arrival Time Worst Slack Calculation Timing Graph Marking Path Extracting Timing Graph Marking Timing Graph Marking Timing Graph Marking Backward Traversing Backward Traversing Backward Traversing Critical Paths Backward Traversing Critical Paths Critical Paths Critical Paths Report Generation Report Generation Report Generation Report Generation 11

Timing Graph Marking  Mark each pair from endpoint to startpoint Endpoint Startpoint 12

Motivation  For each two levels, fanin cone size < fanout cone size – Always mark fanin first to bound fanout region Fanin cone size = fanout cone size 13

Pairwise Marking Start Level End Level Left Level Right Level Fanin cone Fanout cone Overlapped Region (Bounded by fanin cone) 14

Path Searching  Backward traverse nodes in overlapped region  Enhanced by two techniques – Local slack bounds – Slack priority queue  Local slack bounds – Record worst-k slack for each nodes – Bound if current slack is better than slack bound(best slack of the node) – Reduce redundant traversal  Slack priority queue – Obtain globally worst slack node during backward traversing  Use a priority queue prioritized with path slack 15

Runtime & Memory Tradeoff  Perform multiple report_timing concurrently – Without parallelism, slowest runtime/smallest memory usage (100 sec/300MB) – With parallelism, command cache size equals to 2^ 8 to 2^ 14 gives best runtime and memory tradeoff (200 sec/300MB) 16

Scalability  Perform 2^ 21 (1 Million) report_timing in 20 sec/360MB  Runtime increase linearly when command size doubles 17

Thank you! 18

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2018 Contest Results Accuracy Correct Paths Score Runtime Runtime Score Total Total Team 1 100% 3.0 Team 1 128 1.1 Team 2 100% 3.0 Team 2 49 3.0 Documentation Score Memory Memory Score Total Team 1 1.5 Team 1 4854800 0.9 Team 2 2.0 Team 2 2252696 2.0 Totals Score Placement 2 nd Place Team 1 6.6 1 st Place Team 2 10.0 Programmable Solutions Group 20

TAU 2018 Timing Contest on Path Reporting 1st Pr 1s t Prize ize Presented to Pei-Yu Lee, Hsien-Han Cheng, and Iris Hui-Ru Jiang For iTimerP National Chiao Tung University National Taiwan University George Chen Tom Spyrou Song Chen Contest Chair General Chair Technical Chair

TAU 2018 Timing Contest on Path Reporting 2 nd nd Prize rize Presented to Kuan-Ming Lai and Wen-Hung Hsu For BattleCat National Tsing Hua University George Chen Tom Spyrou Song Chen Contest Chair General Chair Technical Chair

Requests Ideas for future contests?  What sort of topics may be interesting to the group? Increasing contestant participation?  How to increase contestants? Increasing committee participation?  We are looking for additional individuals to help plan the contest. Please contact George.J.Chen@intel.com if you are interested! Programmable Solutions Group 23

Acknowledgements Song Xi Tom Chen Chen Spyrou Workshop Contest Workshop Technical Chair Committee General Chair Member TAU 2018 Contestants This contest would not have been successful without your hard work and dedication Programmable Solutions Group 24