On the control of GeO 2 / Ge and On the control of GeO 2 / Ge and metal/ Ge interfaces metal/ Ge interfaces toward metal source/ drain Ge CMOS toward metal source/ drain Ge CMOS Akira Toriumi Department of Materials Engineering The University of Tokyo Tokyo, Japan toriumi@material.t.u-tokyo.ac.jp March 6, 2008 JST-DFG WSP, A. Toriumi 1
New things are not always healthy. New things are not always healthy. Si CMOS spin, phase Si CMOS spin, phase gap gap 2007 2050 non- non -Si Materials Si Materials non- non -Si Materials Si Materials photon, qbit photon, qbit What is a promising candidate for non-Si Materials? We have to take account of not only channel but also contact. March 6, 2008 JST-DFG WSP, A. Toriumi 2
What is the Problem in Si ? What is the Problem in Si ? Si Ｓｉ Microelectronics Research will end in 2015. Si microelectronics is in the metabolic syndrome Si Si Si Requirements for something new Requirements for something new in the next step in the next step Material should be simple. Material should be simple. Operation principle should be simple. Operation principle should be simple. Si Process should be simple. Process should be simple. March 6, 2008 JST-DFG WSP, A. Toriumi 3
Outline Outline 1. Background and Objective Why Ge now ? 2. Ge MIS GeO desorption Ge/GeO 2 MIS Capacitors 3. Ge Schottky Fermi-level Pinning Ohmic contact to n-Ge 4. Ge-CMOS p-MOSFET n-MOSFET 5. Conclusions March 6, 2008 JST-DFG WSP, A. Toriumi 4
Electron Devices in the Next Step Electron Devices in the Next Step FinFET,QW FinFET,QW 3 D Struct ure 3 D Struct ure D evice Pla nar, FD - SOI Sca ling M inia t uriza t ion Pla na r, FD - SOI M inia t uriza t ion Low Pow er Ge, I I I - V, CN T M at eria ls Ge, I I I - V, CN T M at eria ls Si SiGe Ge SOI Ge - FinFET Fin FET March 6, 2008 JST-DFG WSP, A. Toriumi 5
Outline Outline 1. Background and Objective Why Ge now ? 2. Ge MIS GeO desorption Ge/GeO 2 MIS Capacitors 3. Ge Schottky Fermi-level Pinning Ohmic contact to n-Ge 4. Ge-CMOS p-MOSFET n-MOSFET 5. Conclusions March 6, 2008 JST-DFG WSP, A. Toriumi 6
Demand for High Quality GeO 2 /Ge Interface Demand for High Quality GeO 2 /Ge Interface High-k/ Si SiO 2 interface layer is inevitable for good device characteristics. High-k/ Ge An appropriate High-k ? GeO 2 /Ge is thermodynamically unstable. High-k “ high-quality ” GeO 2 / Ge ? metal Ge K. Kita et al., APL 85 (2004) GeO 2 March 6, 2008 JST-DFG WSP, A. Toriumi 7
C- -V Characteristics of GeO V Characteristics of GeO 2 /SiO SiO 2 /Si MIS C 2 / 2 /Si MIS GeO 2 / SiO 2 / Si (N 2 annealing at 600 o C) 0.4 4.8 nm 2 ) Capacitance ( μ F/cm 9.8 nm 0.3 Au GeO 2 0.2 13.4 nm SiO 2 (5nm) Si 0.1 0.0 -3 -2 -1 0 1 2 Gate Voltage (V) H. Nomura et al., IWDTF 2007 March 6, 2008 JST-DFG WSP, A. Toriumi 8
C- -V Characteristics of GeO V Characteristics of GeO 2 2 MIS Capacitors MIS Capacitors C 10nm-thick sputtered GeO 2 after N 2 annealing at 600 o C Normalized Capacitance (C/C MAX ) freq.= 1MHz 1.0 on SiO 2 /Si 0.8 on Si 0.6 0.4 on Ge 0.2 0.0 -3 -2 -1 0 1 2 Gate Voltage (V) K. Kita et al., ECS Trans. 3 (2007) March 6, 2008 JST-DFG WSP, A. Toriumi 9
Evidence of GeO Volatilization from GeO 2 /Ge Evidence of GeO Volatilization from GeO 2 /Ge Thermal desorption spectroscopy （ TDS ） 10 GeO 2 / Ge Intensity (arb.unit) GeO from GeO 2 (25nm) 8 GeO 2 /Ge Ge ( 15nm) SiO 2 (30nm) 6 Si m (GeO) = 4 86,88,89,90 GeO 2 / SiO 2 GeO from 2 GeO 2 /SiO 2 GeO 2 (25nm) SiO 2 (30nm) 0 Si 400 500 600 700 800 o C) Temperature ( S. Suzuki et al., SSDM 2007 March 6, 2008 JST-DFG WSP, A. Toriumi 10
Suppression of GeO Desorption Desorption by Si Cap by Si Capping ping Suppression of GeO 30 GeO 2 /Ge GeO 2 Thickness (nm) Si cap layer 25 WITH Si cap 20 Si (10nm) 15 GeO 2 (25nm) GeO 2 /Ge 10 Ge WITHOUT Si cap 5 N 2 anneal at 600 o C 0 20 40 60 80 Annealing Time (sec) Si capping layer can suppress GeO volatilization. March 6, 2008 JST-DFG WSP, A. Toriumi 11
Dramatic Improvement of GeO 2 /Ge MIS Dramatic Improvement of GeO 2 /Ge MIS Characteristics with Capping ping Layer Layer Characteristics with Cap （ ~ 25nm-thick GeO 2 ， after N 2 600 o C anneal ） 0.20 GeO 2 /Ge with (1MHz) 2 ) Capacitance ( μ F/cm NiSi x Cap 0.15 0.10 0.05 GeO 2 /Ge with Conventional PDA 0.00 -6 -4 -2 0 2 4 6 Gate Voltage (V) S. Suzuki et al., SSDM 2007 March 6, 2008 JST-DFG WSP, A. Toriumi 12
Outline Outline 1. Background and Objective Why Ge now ? 2. Ge MIS GeO desorption Ge/GeO 2 MIS Capacitors 3. Ge Schottky Fermi-level Pinning Ohmic contact to n-Ge 4. Ge-CMOS p-MOSFET n-MOSFET 5. Conclusions March 6, 2008 JST-DFG WSP, A. Toriumi 13
Strong Fermi- -level Pinning at Metal/Ge level Pinning at Metal/Ge Strong Fermi Vacuum Level Vacuum Level 0 0 Energy level from vacuum level (eV) Energy level from vacuum level (eV) 3 3 Y Y Y Y Er Er Er Er Yb Yb b b Y Y La,Sc La,Sc La,Sc La,Sc Hf Hf Hf Hf n + CB CB CB CB CB 4 4 Zr Zr Zr Zr p-Ge Al Al Al Al Ti Ti E G (Ge) Ti Ti E G (Si) VB VB Au Au Au Au 5 5 1) Metal source/drain VB VB VB Ni Ni Ni Ni 2) Low ohmic contact resistance Pt Pt t t P P 6 6 Metal Metal Metal/Si Metal/Si Metal/Si Metal/Ge Metal/Ge T. Nishimura et al., APL (2007) March 6, 2008 JST-DFG WSP, A. Toriumi 14
Interface Modulation Effects Interface Modulation Effects ● without modulation ■ with modulation vacuum metal WF 1. Forming gas annealing 0 Metal: Al 3 Effective work function (eV) (annealing temp. 200~500 º C) Y Er 2. Germanide reaction Metal: Er, Ni Ec CB 4 (annealing temp. 200~500 º C) Al Al (110) (100) (111) 3. Substrate orientation Ev VB FG MGe x Sub. GeO x Metal: Ni Au Ni Ni 5 (Orientation:(100), (110), (111)) March 6, 2008 JST-DFG WSP, A. Toriumi 15
XTEM of NiGe/ Ge(100) I nterface XTEM of NiGe/ Ge(100) I nterface NiGe Ge(100) Still Strong Fermi level Pinning even after Reaction March 6, 2008 JST-DFG WSP, A. Toriumi 16
Unpinned Ge MIS Capacitor Unpinned Ge MIS Capacitor 1.0 1MHz Al 2 O 3 5nm 0.8 2 ) Metal Capacitance ( μ F/cm Al 2 O 3 0.6 Al Ge 0.4 Au 0.2 � Metal dependent V FB 0.0 -3 -2 -1 0 1 Gate Voltage (V) No Fermi Level Pinning thanks to Insulator Insertion No Fermi Level Pinning thanks to Insulator Insertion March 6, 2008 JST-DFG WSP, A. Toriumi 17
Possible Origin of Fermi- -level Pinning level Pinning Possible Origin of Fermi Metal-induced Gap States (MIGS) Formation � Metal wave function penetration � Ge intrinsic properties CBE CNL (This work) Branch Point 4.58 eV 4.63** 4.48* Ge CNL S calc S exp VBE 0.04*** Ge 0.02 * J. Tersoff; PRL 32 (1984) 465. * * M. Cardona and N. Christensen; PRB 35 (1987) 6182. T. Nishimura et al., APL (2007) * * * W. Monch; JVST. B 17 (1999) 1867. March 6, 2008 JST-DFG WSP, A. Toriumi 18
I- -V V Characteristics Characteristics @Al/Ge I @Al/Ge Al Al Ultra-thin Al 2 O 3 Ge Ge n-Ge p-Ge 2 0.3 nm 10 w/o 2 ) Current (A/cm 0 10 40 0.3 nm 20 40 40 40 -2 10 0 20 20 -1 0 1 20 w/o 0 0 0 -1 0 1 -1 0 1 -1 0 1 -4 10 -1 0 1 -1 0 1 V (V) V (V) T. Nishimura et al., submitted. March 6, 2008 JST-DFG WSP, A. Toriumi 19
Outline Outline 1. Background and Objective Why Ge now ? 2. Ge MIS GeO desorption Ge/GeO 2 MIS Capacitors 3. Ge Schottky Fermi-level Pinning Ohmic contact to n-Ge 4. Ge-CMOS p-MOSFET n-MOSFET 5. Conclusions March 6, 2008 JST-DFG WSP, A. Toriumi 20
Metal source/ drain p p- -ch ch Ge MOSFET Ge MOSFET Metal source/ drain Metal source/ drain p-ch Ge(100) MOSFET p-MOSFET GeO 2 p-MOSFET GeO 2 W/L=530 μ m/ 190 μ m W/L=530 μ m/ 190 μ m 20 20 V gs -V th = -0.8 V V gs -V th = -0.8 V FUSI FUSI 15 15 LYO or GeO 2 GeO 2 -0.6 V -0.6 V PtGe PtGe I s ( μ A ) I s ( μ A ) 10 10 n-Ge n-Ge -0.4 V -0.4 V 5 5 0 V 0 V -0.2 V -0.2 V 0 0 -1.0 -1.0 -0.5 -0.5 0.0 0.0 V ds (V) V ds (V) No I mpurity Doping ! T. Takahashi et al., iedm2007 March 6, 2008 JST-DFG WSP, A. Toriumi 21
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