From physics to products From MRAM to MLU and beyond memory M - PowerPoint PPT Presentation

From physics to products From MRAM to MLU and beyond memory M agnetic R andom A ccess M emory M agnetic L ogic U nit Lucien Lombard Crocus-Technology

Overview • 1 - The semiconductor industry • 2 - Crocus-Technology • 3 - MRAM Technology • 4 - From the Lab to the Fab challenges of industrial products • 5 - From TAS to MLU • 6 - Product developments • 7 - Conclusion

The semiconductor industry Assembly of companies engaged in the design and fabrication of integrated circuit. • Generate ~$300 billions revenue (year2010). • Formed around 1960. • Principle : use semiconductor material to realise transistor based integrated circuits. CPU, Memory, amplifiers ,… M2 Industry dominated by US, Japan and South Korea V2 M1 • V1 What bring semiconductor devices : • M0 Low Power comsumption and power dissipation Standard CMOS Wafer • High reliability • Small size  allow IC miniaturization Note : IC = Integrated Circuit CMOS = Complementary Metal-Oxide Semi-conductor

The semiconductor industry An Industry organized to follow a Very Agressive Roadmap over the last 40 years!!  higher performances at reduced cost to increase profits • Technology node shrinked from 10µm to 10nm • Wafer size increased from 50mm to 300mm (450mm wafers in a few years) How to continue this road map? What can be done beyond CMOS? For futher reference see the International Technology Roadmap for Semiconductors @ http://www.itrs.net

Key Milestones Partnership with Leaders 2006/2008  Crocus funded: CEA/LETI/Spintec LETI  MRAM development: SVTC 300mm LETI SPINTEC 200mm 2009 MINATEC  Manufacturing - Tower Jazz @ 130nm Clean room 2010/2012  Invent MLU: MIP – Logic  $250M JV: CNE @ 90nm-65nm-45nm  JDA with IBM: MLU deployment Business development  with Morpho: Smartcard  with Inside secure  with SMIC: CMOS supply 5

Corporate Profile - Powerful Ecosystem Technology: R&D Partners: Magnetic Logic Unit (MLU TM ) IBM JDA – Yorktown > 150 patents CEA - Grenoble > Memory blocks, Logic, Analog Product Focus: MCU Manufacturing Partners: Smartcards/Secure MCU Crocus Nano Electronics High temperature Tower Jazz Smart sensors amplifiers SMIC NV-SRAM Strong team: Investors: 50 Employees $125M cash raised »200 Associated persons Committed Syndicate 6

Operations Santa Clara, CA (USA) Grenoble (France) Russia Design, Integration, R&D, Magnetic Materials Crocus Nano Electronics Test, Sales & Marketing Processing Manufacturing Partners: SVTC Migdal Haemek (Israel) Tower Semiconductor Commercial Foundry 7

What is MRAM? Disk Drive: Semiconductor: Magnetic Technology Speed & Logic CMOS (20 years of technology experience) Value Add 3 masks MRAM Integrated Magnetic Bits 25-40 Mask Layers CMOS LOGIC 8

Technology: Process Schematic 4- Preparation final interconnect 3- Dielectric refill AL Pads MRAM 2- Magnetic layers etch M4 Bit-Line 1- Magnetic layers deposition V4 MM1 0-Surface preparation MM2 - Strap V M1 M3 4- Connection to MRAM CMOS 3- Last Metal preparation V3 2- Multilayer metal 1- CMOS frontend M2 V2 M1 V1 M0 Standard CMOS Wafer

The search for the “universal memory” The Universal Memory: - Non volatile - Fast as SRAM - Dense as DRAM - Infinite endurance - Easy / cheap to embed into ASIC - Zero stand-by current - Fully scalable

MRAM vs. other Memories NO NO YES YES YES YES YES 4Gb 128Mb 32Gb 2Gb 16Mb 16Mb>8Gb 512Mb 10ns 5ns 1000ns 1000ns 100ns 15ns 100ns 10ns 5ns 1000ns 50ns 15ns 15ns 15ns 10**16 10**16 10**3 10**4 10**10 10**12+ 10**6 NO NO YES YES NO Yes ? 6F² 80F² 4F² 10F² 30F² 8-25F² 10F² 11

the Quest… THE Universal Memory High Non Volatile Density NAND MRAM MRAM DRAM NAND SRAM SRAM DRAM High SRAM NAND MRAM Performance DRAM 12

MRAM Field of Use • FPGA • TRANSPORTATION $ MARKET OPPORTUNITY*** • SMART CARD • HANDSET $80B • Advanced uCONTROLLER • BB-SRAM $20B • INDUSTRIAL • DEFENSE • DRAM Replacement • uCONTROLLER • SRAM Replacement • SEARCH ENGINE $2B 4 – 8 YEARS 0 – 4 YEARS 8+ YEARS *** Source: industry data quest 13

MTJ: the heart of MRAM bit cell R   MTJ structure R R   TMR « 1 » R Soft ferromagnet  Insulating barrier Hard ferromagnet Pinning layer « 0 » H storage reference Field Line Parallel moments Anti-parallel moments MTJ Field Line low R state high R state Memory cell

Scaling : the stability issue Switching rate Stored magnetic energy KV    k T e B Thermal energy 0 ( 0 = 10 -9 s) Switching probability t      P 1 e  10 years retention  KV/k B T>60 As V goes down tendency to self-demagnetize gets worst Feature size  Superparamagnetic limit V  (also observed in HDDs) Only solution is to increase barrier height ? Stability Writability  The « storage trilemna » KV=cte  K  K 

There are many MRAMs ! Field-driven STT (SPRAM) DW motion Planar Perpendicular H x H y Thermally Assisted (TAS) STT-TAS Precessional STT Domain Wall motion

TAS-MRAM Thermally assisted writing  Use of an additional AF material to “lock” the stored data: storage layer is an F/AF exchange biased bilayer: high stability @ small feature size  The data can be “unlocked” by locally heating the memory cell - use current flowing through the junction to heat the storage layer above its blocking temperature: perfect selectivity ON OFF  Switch the storage layer by a single magnetic field AF AF low T B F decoupled storage F H reference high T B T B T

TAS writing   H sw  I sw I h ≈ ≈ ≈ ≈ OFF OFF ON OFF ON heating writing cooling 1 state 0 state R 1 R R H sw H ex H ex H H H I h = 0 I h > 0 I h = 0 I sw = 0 0 I sw > 0 I sw = 0 T  writing temperature T = room temperature T = room temperature Step 1 : Heat cell by flowing Step 2 : Switch magnetization by Step 3 : Cool under current through transistor a magnetic field pulse magnetic field

From MRAM to MLU: Stability TAS MRAM Perpendicular STT Planar STT Other MRAM Toggle FIMS KV/kT (Stability) 19

Technology: Process Roadmap Tower IBM/CNE GENERATION 2 GENERATION 3 GENERATION 4 GENERATION 1 TBD 100nm 200nm Tunnel 90nm Oxide LOCAL 50nm STRAP STRAP STRAP STRAP FL Field Line Field Line Field Line CD 200nm 90nm/65nm/45nm 120nm 28nm/15nm 30mA 2mA 500uA 20mA IField 2A 500uA ITAS 100uA 25uA Strap Strap Arch Thin Strap Thin strap + 2 Mask Masks + 2 Masks + 4 Masks + 4 Masks

Technology: Magnetic materials Contact layer Thermal barrier Etch stop layer NiFe (3) SL IrMn (6.5) CoFe (2) MgO (1.1) RL PtMn (20) CoFeB (2) Ru (0.8) CoFe (2) Buffer layer Timaris sputtering tool from SINGULUS 200mm wafers Installed at Minatec, Grenoble

Technology: Thermal Management Top Thermal Barrier Std MRAM TAS AF stack storage reference Bottom Thermal Barrier Compared to Standard MRAM, stack changes are : – Add anti-ferromagnetic layer – Add thermal barriers • Concentrate heat • Control temperature rise • Reduce heating power

Gen2 vs. Gen3

Technology: Process Schematic 4- Preparation final interconnect 3- Dielectric refill AL Pads MRAM 2- Magnetic layers etch M4 Bit-Line 1- Magnetic layers deposition V4 MM1 0-Surface preparation MM2 - Strap VM1 M3 4- Connection to MRAM 90nm/65nm 3- Last Metal preparation V3 2- Multilayer metal CMOS 1- CMOS frontend M2 V2 M1 V1 M0 Standard CMOS Wafer

Technology: GEN 3 PROCESS FLOW M3 Copper • Receive CMOS wafer from Foundry after M3 dielectric deposition • Metal trench Litho and etch • Cladding deposition (PVD). Co • Cu Damanscene (PVD) Std Cu seed M3 • Top Cladding Deposition (PVD) Ta • CMP Top Cladding metal M3 M3 25

GEN 3 PROCESS FLOW • Deposit Dielectric and open Via • Deposit Strap Metal (PVD). Ta M3 • Pattern Strap Metal M3 • Etch Strap Metal 26

GEN 3 PROCESS FLOW • Deposit Magnetic Stack (PVD) -Total of 10 -12 thin layers. 7 to 8 different materials : Ta, Ru, FeMn, CoFe, CoFeB, Mgo, NiFe - Precise thickness and film morphology M3 control • Magnetic Stack Etch - Precise side wall control - No redeposition and short M3 - Post shape control - Magnetic film affected by Cl and F etch 27

GEN 3 PROCESS FLOW • Dielectric Deposition M3 • Via First Cu Dual Damanscene M4 M4 process (PVD) Ta, TaN, Cu seed V3 M3 28

GEN 3 PROCESS FLOW • Final dielectric layer deposition • Ta and AlCu deposition (PVD) • AlCu Pad etch Al Cu Pad M4 M4 V3 M3 29

From the Lab to the Fab : The challenges for functional products Functional device over 10 years and 10 12 write cycles : Yield for Read Head production : 1 device = 1 MTJ  40% bit yield on a wafer is enough to make profits. For one functional one 1Mb MRAM, bit yield within this memory has to be >99,9999% Objective of Reliability + Yield : 1Mb TAS-MRAM  Errors rate <10 -6 over 10 years and 10 12 write cycles

From MRAM to MLU Magnetic Unit Logic

From MRAM to MLU Magnetic Unit Logic MULTI-BIT MRAM How Magnetic Logic accelerates innovation ? L-Cell MRAM MLU SECURITY CHIP Magnetic Logic Search Logic Magnetic Sensors* CMOS based 32 * No CMOS required