Fr Front t End Bo Board Requirements, Speci cification and QA/ QA/QC QC Alexander Singovski, L4 FE manager PreFinal Design Review Dec. 12-14, 2018 Alexander Singovski ECAL FE board NSF Pre-FDR Assessment Dec. 12-14, 2018 p. 1
Outline § Manager and engineering team bio § Requirements and specifications § Interface control § Design and Prototyping § QA/QC plan Alexander Singovski ECAL FE board NSF Pre-FDR Assessment Dec. 12-14, 2018 p. 2
Project Manager Alxander Singovski § Education: Moscow Institute of Physics and Technology, PhD on experimental particle physics, IHEP Protvino, Russia § Current position: Physicist, University of Notre Dame § Relevant experience • Deputy Spokesman of WA102 experiment at CERN (Glueball search at CERN Omega facility) Responsible for the hardware and data analysis software of the lead-glass • electromagnetic calorimeter • CMS ECAL Optical Links and Low Voltage projects coordinator Design, production and testing of the CMS ECAL on-detector data transmission • and control units: Giga Opto-Hybrids (GOH) and Token Ring Link boards • CMS ECAL Beam Tests coordinator • CMS ECAL Upgrade coordinator 2010-2014 Fundamental study of the CMS ECAL component longevity and radiation • tolerance Alexander Singovski ECAL FE board NSF Pre-FDR Assessment Dec. 12-14, 2018 p. 3
Engineering Team Alexander Dolgopolov Current Position: Electronic Engineer, University of Notre Dame Professional qualification: Moscow State University of Instrument Engineering and Computer Science Relevant experience: • ADC system COMPASS experiment at CERN • Design and tests of GOL opto-hybrids, ECAL FE card • Design and tests of ECAL on-detector Token Ring boards Nikitas Loukas Current position: Electronic Engineer, University of Notre Dame Professional qualification: PhD in electronic engineering, University of Ioannina, Greece Relevant experience: CMS member for 6 years. • • Barrel muon trigger development. • Responsible for the ECAL Barrel Calorimeter Processor (BCP) design Alexander Singovski ECAL FE board NSF Pre-FDR Assessment Dec. 12-14, 2018 p. 4
Requirements & specifications BCAL-engr-001 § Should serve one Trigger tower: 5x5 crystals, 5 VFE boards BCAL-engr-008 § Should fit to the legacy FE card dimensions BCAL-sci-engr-002 § Should fit to the HL-LHC radiation environment BCAL-sci-engr-001 1 Mrad § 10 4 n/cm 2 § § Should stream the data generated by five VFE boards off-detector with no BCAL-sci-engr-004 loss BCAL-engr-040 Total data rate ~40Gb/s § § Should deliver high precision (<10ps jitter) clock to VFE components § Should provide data flow synchronization: transmit synch. Commands BCAL-engr-010 from off-detector to VFE with the fixed latency § Should provide slow control functions required by VFE and LVR boards configuration registers setting (I2C interface) § Power voltage monitoring § Temperature monitoring § Alexander Singovski ECAL FE board NSF Pre-FDR Assessment Dec. 12-14, 2018 p. 5
Scope of the project ECAL legacy on-detector electronics ECAL Upgrade on-detector electronics Optical transmitters 2x 0.8Gbps (GOL) Optical transmitters 8x4.8Gbps (GBTx) or 4x 10.24Gbps (lpGBT) Level 1 trigger Level 1 trigger Data rates: Per Trigger Tower : Per Trigger Tower : Per VFE card : Per crystal : Per VFE card : • 5 VFE cards • 5 VFE cards 5 crystals Pre-amp 3 ranges 5 crystals • • • 52Gbps @ 160 MHz • • 14Gbps @ 40 MHz 10.4Gbps @ 160 MHz 12 bit ADC 2.8Gbps @ • • • 27Gbps @ 160Mhz @ à 0.8Gbps TRIGGER • • 5.4Gbps @ 160Mhz @ 14 bit data @ 40 MHz 40 MHz • • compression primitives compression 560 Mbps data flow sampling • L1 trigger à 0.8Gbps • DATA Alexander Singovski ECAL FE board NSF Pre-FDR Assessment Dec. 12-14, 2018 p. 6
FE Interfaces 7 I2C Masters § 25 +3 clock lines all from Master lpGBT § 25 control down e-links, one per LiTe-DTU § 20 Power voltage monitoring: 2 per VFE, 7 LVR § 30 thermal sensors § Alexander Singovski ECAL FE board NSF Pre-FDR Assessment Dec. 12-14, 2018 p. 7
Interface Control Upgrade LVR card project Resp: W.Lusterman ETH, Zurich Upgrade VFE card project Upgrade FE card project Upgrade Barrel Resp: W.Lusterman Resp: A.Singovski, Calorimeter Processor ETH, Zurich University of Notre Dame project Resp: N.Loukas University of Notre Dame All L4 Projects managers are CERN-based • 7 I2C Masters § Regular project discussions at the ECAL Upgrade • 25 +3 clock lines all from Master lpGBT § meetings 25 control down e-links, one per LiTe-DTU § Close personal contacts • 20 Power voltage monitoring: 2 per VFE, 7 LVR § Documentation storage at the CERN EDMS • 30 thermal sensors § Alexander Singovski ECAL FE board NSF Pre-FDR Assessment Dec. 12-14, 2018 p. 8
Upgrade FE card design Legacy ECAL FE card § dimensions 4 lpGBT chips § One 4T1Rx Versatile_Link+ § hybrid Enough surface to place 7 § lpGBT and 2 4T1R, plus optional DC-DC converter, plus optional GBT -SCA Comfortable tracing for § baseline option: 4 lpGBT & 1 4T1Rx Major challenge – 4-7 e-links § @ 320Mbps per DTU è 100 - 175 total Alexander Singovski ECAL FE board NSF Pre-FDR Assessment Dec. 12-14, 2018 p. 9
GBT (2010-2015) Dedicated chipset for the high speed § data transmission, compatible with HL-LHC environment Efficient error correction protocol § Bandwidth 5 Gb/s § User data rate 3.36Gb/s § § Radiation tolerance Gamma – 100 Mrad § Neutrons 10 5 n/cm 2 § § Available in big quantities. Mass production ended in 2015 Alexander Singovski ECAL FE board NSF Pre-FDR Assessment Dec. 12-14, 2018 p. 10
lpGBT lpGBT project schedule Components description available for users. Start of the Prototype2 design Limited number of chips for users. Pritotype2 What’s the lpGBT? production Alexander Singovski ECAL FE board NSF Pre-FDR Assessment Dec. 12-14, 2018 p. 11
Prototyping Schedule § Prototype 0: “FE demonstrator”, Q4 2017 1 VTRx & 1 VTTx VL module, • Can receive data from 5 legacy VFE (one VFE-FE data channel fully functional, one – partially) • Used during 2017-2018 beam tests to get spikes data sample (analysis on-going) • § Prototype 1 “smart” GBTx – based EF card, Q2 2018 1 VTRx & 2VTTx VL modules, • Will receive data from 5 legacy or upgrade VFE • Clock to VFE from one source • I2C via optical down-link • § Prototype 2: Realistic lpGBT – based FE card Q4 2019 V4T1Rx+ VL+ optical module • Optimal clock to VFE distribution • Both lpGBT chain and GBT-SCA control options • Both multi-node down e-link and 1-to-5 fanout • § Prototype 3: final configuration Q1 2020 V4T1Rx+ VL+ optical module • Optimal clock to VFE distribution • Final control design • Alexander Singovski ECAL FE board NSF Pre-FDR Assessment Dec. 12-14, 2018 p. 12
Demo Board(2017) Readout via mTCA backend prototype Alexander Singovski ECAL FE board NSF Pre-FDR Assessment Dec. 12-14, 2018 p. 13
Demo board outcome § First experience with the CERN custom fast data link components: GBTx chipset and Versatile Link hybrids § Implementation of the specific clock distribution for the high speed serial links § Definition of the initialization and configuration sequence § Definition of the required PCB and assembly quality § Beam tests: data transfer from the legacy VFE to the mTCA upgrade off-detector units prototypes § Definition of the Prototype1 design Alexander Singovski ECAL FE board NSF Pre-FDR Assessment Dec. 12-14, 2018 p. 14
Prototype Board V1 (2018) Power Several options for system clock to Slave GBTx, § input including recovered and e-link clock from I2C GBTx Master GBTx GBTx GBTx E-link clock to VFE from Master GBTx § slaves Configurable interface to VFE: e-links @ (80, § VL TTx 160 or 320) Mbps GBTx Electrical and optical I2C § configuration GBTx VL TTx Can be connected to § Legacy VFE via Adapter card • Upgrade VFE either directly or via VL TRx • e-link clk OUT Adapter card GBT- GBTx GBTx Max data rate: 5x3.36=16.8Gbps § SCA Can transmit data from: § Ref clk IN 5 legacy VFE @ 40Mhz clock • 1 DTU per Upgrade VFE @ 160MHz clock • I2C GBTx master I2C GBT-SCA without Adapter 5 Upgrade VFE @ 160MHz with buffer in • Adapter VFE connectors Can be powered either from Upgrade LVR card § or from external power supply Alexander Singovski ECAL FE board NSF Pre-FDR Assessment Dec. 12-14, 2018 p. 15
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