Flexible Timing Simulation of RISC-V Processors with Sniper Neet - PowerPoint PPT Presentation

Flexible Timing Simulation of RISC-V Processors with Sniper Neet eethu B Bal al M Mal ally lya 1 , Cecilia Gonzalez-Alvarez 2 , Trevor E. Carlson 1 1 National University of Singapore, Singapore 2 Ghent University, Belgium

Outline • Need for Simulation • Sniper Simulator Overview • Our enhancements to Sniper • Initial Processor Performance Analysis • Conclusion 2/6/2018 2

Why do we need Simulation? Performance analysis of next-generation systems Architecture design space exploration Pre-silicon software optimizations 2/6/2018 3

Trade-offs in Simulation Verilog/RTL High-level 2/6/2018 4

Trade-offs in Simulation Verilog/RTL High-level Efficient MLP processor Instr. Queue ALUs Commit Learn Fetch Decode and Writeback Slice Bypass Caches Queue Source: T.E.Carlson, et al., “ Load Slice Core ” [ISCA2015] 2/6/2018 5

Sniper Simulator – An Overview • Parallel simulator based on Interval Simulation • Models multi-/many-cores running multithreaded 1 and multi-program workloads • Hardware validated for x86 • Flexible simulation options 1 Currently not supported for RISCV 2/6/2018 6

Sniper – Beyond Traditional Simulation • Strong adoption in industry and academia • 550+ citations • 800+ researcher downloads • 64+ countries • Actively used since 2011 • Belgium-based team • Supports next generation Xeon Phi (KNL++) • HiPEAC TechTransfer Award 2/6/2018 7

Sniper – Key Differentiators • Fast development time Almost 10 MIPS • Enables Limit Studies 1000 cores • Branch Prediction • Memory Dependence Prediction • Shared Multi-level Cache Hierarchy Average error of just 11% • High Performance and Scalability with HW 2/6/2018 8

Sniper - Interacting with the Simulator $SNIPER_HOME/include/sim_api.h • Python interfaces • SimAPI • Magic Instructions • SimROIStart() - SimROIEnd() 2/6/2018 9

Sniper - Interacting with the Simulator • Energy Stats Run McPAT Update the statistics 2/6/2018 10

Sniper - Interacting with the Simulator • Loop Tracer cycles instructions 2/6/2018 11

Sniper + RISC-V ecosystem • RISC-V • Open, Extensible ISA • Collection of related software tools • Existing Architecture-level Software implementations • Functional simulators Spike rv8 • Many additional things 2/6/2018 12

Comparison with existing solutions Sniper + RISC-V gem5 (RISC5) FireSim / Chisel / Verilog Development C++ based (SW) C++ based (HW) RTL based (HW) Methodology Dev-time +++ ++ + Sim-time +++ ++ ++++/+/+ Simulation Cycle-level + Cycle- Cycle-level Cycle-exact + Cycle-approximate model approximate Requires RTL/ Flexibility Ease-of-use / modification abstract models Fidelity Sophisticated models require hardware Cycle-exact models derived from validation synthesizable RTL 2/6/2018 13

Simulation Flow Sniper Short Final RTL Dev Testing Check Validation Only Short Final RTL Development Testing Check 2/6/2018 14

Sniper Architecture Sniper Frontend Sniper Backend Decoder Emulation/ Binary Core Cache Library SIFT pipes Performance Performance Instrumentation Models Models events thread 1 SIFT 1 Core Model 1 L1 Thread Scheduler L2 events thread 2 SIFT 2 Core Model 2 L1 … … … NoC Core Model M-1 L1 events thread M-1 SIFT M-1 L2 Core Model M L1 events thread M SIFT M 2/6/2018 15

How did we enhance Sniper? Sniper Frontend Sniper Backend Decoder Emulation/ Binary Core Cache Library SIFT pipes Performance Performance Instrumentation Models Models events thread 1 SIFT 1 Core Model 1 L1 Thread Scheduler L2 SIFT 2 events thread 2 Core Model 2 L1 … … … NoC Core Model M-1 L1 SIFT M-1 events thread M-1 L2 Core Model M L1 SIFT M events thread M 2/6/2018 16

How did we enhance Sniper? RISC-V functional simulators - rv8 / 1 Spike were updated to support SIFT Frontend Backend generation SIFT 2 1 pipes Decoder Library 3 2 Architectural agnostic methods 4 … … … were added to implement the decoding phase of the processor Core Model 3 Parameters like description of Configuration files 4 ports/ functional units, latencies, to resemble a BOOM processor etc. were updated 2/6/2018 17

Sniper Instruction Trace File Format (SIFT) • Dynamic Instruction stream generated by the Frontend Instruction Execution Order Memory Addresses for Loads and Stores Dynamic Branch Directions (taken/not taken) Executed/masked info for Predicated instructions 2/6/2018 18

How to add new Frontend? Control Sift::Writer::Magic() Instruction Instrumentation Sift::Writer::InstructionCount() Sift::Writer::CacheOnly() Sift::Writer::Instruction() // addresses, branch direction, etc. 2/6/2018 19

How to add new Frontend? rv8 / Spike 2/6/2018 20

How to add new Frontend? rv8 / Spike SIFT rv8 / Spike Sift::Writer Frontend Backend SIFT pipes … … … 2/6/2018 21

How to update Backend? • Decoder Library $SNIPER_HOME/decoder_lib • 2 classes • Decoder • InstructionDecoded • Core Model $SNIPER_HOME/common/performance_model • Config Files $SNIPER_HOME/config 2/6/2018 22

How to run Sniper ? ./run-sniper --frontend=[pin|dr|spike|rv8|legacy] --config [SNIPER] Start [SNIPER] -------------------------------------------------------------------------------- [SNIPER] Sniper using SIFT/trace-driven frontend [SNIPER] Running full application in DETAILED mode [SNIPER] -------------------------------------------------------------------------------- [SNIPER] Enabling performance models [SNIPER] Setting instrumentation mode to DETAILED Trace Monitor Started [TRACE:0] -- DONE -- [SNIPER] Disabling performance models [SNIPER] Leaving ROI after 18.26 seconds OUT: RUN: TraceThread [SNIPER] Simulated 5.0M instructions, 11.2M cycles, 0.45 IPC [SNIPER] Simulation speed 273.4 KIPS (273.4 KIPS / target core - 3657.1ns/instr) [SNIPER] Setting instrumentation mode to FAST_FORWARD [SNIPER] End [SNIPER] Elapsed time: 18.41 seconds 2/6/2018 23

Experimental Setup • Sniper multi-core simulator • Similar to BOOM v1 DefaultConfig • Dispatch width:2, Issue Width:3, ROB:80 • 32KB L1s, 1MB L2 • 2.0GHz • SPEC CPU2006 benchmarks • First 5M instructions 2/6/2018 24

Initial Processor Performance Analysis Testcase IPC KIPS 130.87 130.96 470.lbm 0.15 97.899 444.namd 1 304.719 450.soplex 1.52 343.668 456.hmmer 2.71 523.41 462.libquantum 2.65 611.968 Source: Tuan Ta, et. al, “ Simulating Multi-Core RISC-V Systems in gem5 ”, [CARRV 2018] 2/6/2018 25

Conclusion • An infrastructure extension of Sniper • Sniper + RISC-V is now available • Next steps • Improve the simulator features to allow for a detailed comparison with cycle-level processor implementations 2/6/2018 26

• Thank you • Download Today! • http://snipersim.org/w/Download • Questions? • http://groups.google.com/group/snipersim 2/6/2018 27

Flexible Timing Simulation of RISC-V Processors with Sniper Neet eethu B Bal al M Mal ally lya 1 , Cecilia Gonzalez-Alvarez 2 , Trevor E. Carlson 1 1 National University of Singapore, Singapore 2 Ghent University, Belgium