Fault Injection Characterization on ARM Cortex-A9 George - - PowerPoint PPT Presentation

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Fault Injection Characterization on ARM Cortex-A9 George - - PowerPoint PPT Presentation

Mar 23, 2023 243 likes •524 views

ElectroMagnetic Fault Injection Characterization on ARM Cortex-A9 George Thessalonikefs George.Thessalonikefs@os3.nl University of Amsterdam February 5, 2014 Introduction Hardware Fault Injection Induce faults to hardware through side

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SLIDE 1

ElectroMagnetic Fault Injection Characterization

  • n ARM Cortex-A9

George Thessalonikefs

George.Thessalonikefs@os3.nl University of Amsterdam February 5, 2014

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SLIDE 2

Introduction

Hardware Fault Injection

Induce faults to hardware through side channels:

  • Clock
  • Power supply
  • Electromagnetic radiation
  • Light
  • Temperature

Goals

  • Change behavior
  • Change data

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ElectroMagnetic Fault Injection

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For inducing a significant voltage spike, distance d < D

Source: Riscure

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EMFI vs VCC & Optical FI

No preparation needed for the target

  • VCC FI : Need to work with capacitors to glitch

the core voltage line

  • Optical FI : Decapsulation of the chip

Countermeasures for:

  • VCC FI: Glitch sensors
  • Optical FI: Light sensors

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Picture: Decapsulated chip

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SLIDE 5

EMFI in action

http://www.youtube.com/watch?v=dew0KD_-ypw

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SLIDE 6

Research question

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What are the effects of ElectroMagnetic Fault Injection (EMFI) on embedded chips?

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SLIDE 7

Setup

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Setup

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Target

Wandboard SOLO

Freescale i.MX6 Solo Processor Using an ARM Cortex-A9 Single Core

Specifications:

  • 32-bit processor
  • ARMv7 architecture based on RISC
  • Clock speed of 792 MHz:

1,26 ns/cycle

  • Pipeline
  • Dual-issue superscalar
  • Out-of-order
  • Speculative execution
  • 8-stage

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Dual-issue superscalar Pipeline

Example:

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http://en.wikipedia.org/wiki/File:Superscalarpipeline.svg

IF: Instruction Fetch ID: Instruction Decode EX: Execute MEM: Memory access WB: Write Back

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SLIDE 11

ARM Cortex-A9 Pipeline

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http://www.arm.com/images/A9-Pipeline-hres.jpg

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SLIDE 12

Code instrumentation

  • Initialize registers to known values
  • Trigger ON
  • Critical area code
  • Trigger OFF
  • Print results

Code was written in ARM assembly to avoid C compiler’s optimization

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SLIDE 13

Critical area code

  • R0 initialized to 0xFFFFFFFF
  • R1 initialized to 0x00000001
  • Unrolled loop of 32 pairs of instructions:
  • Logical operation
  • Shift R1 1-bit to the left

Logical operations:

  • BIC (BIt Clear)
  • EOR (Exclusive OR)

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SLIDE 14

Visualization of fault injection

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Blue line: Trigger signal Red line: Coil current

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SLIDE 15

Correct Output

BIC version

R0: 00000000 R1: 80000000 R2: FFFFFFFF R3: 020B4000 R4: A54444A5 R5: A55555A5 R6: A56666A5 …….

EOR version

R0: 00000000 R1: 80000000 R2: FFFFFFFF R3: 020B4000 R4: A54444A5 R5: A55555A5 R6: A56666A5 …….

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Full chip detailed scan

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Die detailed scan

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Glitches with desired results

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Glitch results

Logical operation not executed

  • Suspects:
  • Instruction Fetch
  • Instruction Execution
  • Write back

Expected result: R0: 00000000 R1: 80000000 Glitched result: R0: 00000001 R1: 80000000

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SLIDE 20

Glitch results

Logical shift not executed

  • Suspects:
  • Instruction Fetch
  • Instruction Execution
  • Write back

Expected result: R0: 00000000 R1: 80000000 Glitched result: R0: 80000000 R1: 40000000

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SLIDE 21

Glitch results

Logical operation and Logical shift not executed

  • Suspects:
  • Instruction Fetch
  • Instruction Execution
  • Write back

Expected result: R0: 00000000 R1: 80000000 Glitched result: R0: 80000001 R1: 40000000

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SLIDE 22

Glitch results

Data abort exception due to unaligned access

  • Suspects:
  • PC register glitched
  • Stack corrupted

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Glitch results

Prefetch abort exception due to non-existing memory regions

  • Suspects:
  • PC register glitched
  • Stack corrupted

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Conclusion

  • Edges of the chip more sensitive than the top of

the die

  • No unused register corruptions
  • Difficult to constantly have the same results with

EMFI

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SLIDE 25

Future work

  • Comparison of full area scans of the package

between ALU and memory instructions

  • Research the impact of EMFI on jump

commands

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SLIDE 26

Thank you

Questions?

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