Experiences Using a Novel Python-Based Hardware Modeling Framework - PowerPoint PPT Presentation

Experiences Using a Novel Python-Based Hardware Modeling Framework for Computer Architecture Test Chips Experiences Using a Novel Python-Based Hardware Modeling Framework for Computer Architecture Test Chips This Poster... What Does PyMTL Enable? Describes a taped-out 2x2 mm 1.3M-transistor Test Test Test Test Harness Harness Harness Harness test chip in IBM 130nm designed and implemented using PyMTL, a novel Python-based hardware modeling framework Verilog' Verilog FL CL RTL RTL' RTL Model Model Model Model Model' Goal of tapeout was to demonstrate the ability of this framework to enable Agile hardware design flows 1. Incremental refinement 2. Automated testing from algorithm to and integration of hardware implementation PyMTL-generated Verilog PyMTL: A Unified Python-Based Framework for FL, CL, and RTL Modeling Functional-Level Modeling (FL) FL CL RTL Model Model Model - Behavior Cycle-Level Modeling (CL) 3. Multi-level co-simulation of FL, CL, and RTL models - Behavior - Cycle-Approximate - Analytical Area, Energy, Timing Verilog Register-Transfer-Level Modeling (RTL) RTL - Behavior Model - Cycle-Accurate Timing - Gate-Level Area, Energy, Timing 4. Construction of highly parameterized RTL chip generators Cornell University Christopher Torng 1 / 4

Experiences Using a Novel Python-Based Hardware Modeling Framework for Computer Architecture Test Chips PyMTL for Computer Architecture Test Chips Why Build Computer Architecture Test Chips? PyMTL for Agile Hardware Design PyMTL Highly Automated Key Aspect of Agile Hardware Design Framework Standard-Cell Design Flow - Rapid design iteration Big tape-out - "Building the right thing" FL Simulation Small tape-out - Reduces cost of validation CL Simulation Tape-in RTL Simulation ASIC flow Benefits Research FPGA Synthesis - Builds research credibility Post-Synthesis C++ - Highly reliable power and Gate-Level Simulation energy estimates for new Floorplanning architecture techniques Power Routing * Adapted from Yunsup Lee IEEE Micro 2016 Placement Design Methodologies: Large Chips vs. Small Chips Clock Tree Synthesis Routing Large-Scale Commercial Chips Post-Place-and-Route - High-volume and high-yield production Gate-Level Simulation - Overcome design challenges with large teams Power Analysis Computer Architecture Test Chips DRC LVS RCX - Low-volume and reasonable-yield production Transistor-Level Sim - Overcome design challenges despite small teams and limited resources Tape Out Provide small teams with highly productive Small teams push RTL to layout with development frameworks to shorten time to tapeout validated gate-level netlist within a day Cornell University Christopher Torng 2 / 4

Experiences Using a Novel Python-Based Hardware Modeling Framework for Computer Architecture Test Chips Detailed Methodology PyMTL Using PyMTL for Agile Hardware Design PyMTL FL / CL Models C-Based HLS PyMTL Verilog Import Commercial Verilog RTL of PyMTL RTL of Full Design Accelerator HLS Tool Accelerator Tested in C Verilog RTL Modules PyMTL to Commercial Specially Annotated Verilog Translator PyMTL-Driven Xilinx-Based FPGA for FPGA Synthesis Testing Framework FPGA Tools Verilog RTL PyMTL Verilog Import PyMTL Simulator of Full Design w/ Unit Tests and FPGA Logic Assembly Test Suite w/ Full Design SRAM Specification Mature full-featured software testing tools Synopsys SRAM Macros VCD IBM 130nm Design Compiler SRAM Compiler Front-End Views Traces Standard Cell Post-Synthesis Front-End Views GDS of Synopsys vcat utility ASIC Gate-Level Netlist SRAM Macros Standard / Pad Cell Synopsys Verilog Gate- Back-End Views IC Compiler Level Simulator IBM 130nm PDK Post-PAR GDS of Full Design Calibre LVS Gate-Level Netlist Full-Custom LVDS Receiver DRC-Clean GDS Tapeout-Ready GDS GDS & LEF Calibre DRC of Full Design of Full Design Cornell University Christopher Torng 3 / 4

Experiences Using a Novel Python-Based Hardware Modeling Framework for Computer Architecture Test Chips PyMTL in Practice: BRG Test Chip 1 divided clk out clk out clk out debug LVDS LVDS Taped out in March 2016 reset Expected return in Fall 2016 diff clk (+) LVDS clk Recv div diff clk ( − ) reset single tree clk tree ended clk Ctrl host2chip Host RISC Sort Reg Interface Core Accel chip2host Memory Arbitration Unit SRAM SRAM SRAM SRAM Bank Bank Bank Bank (2KB) (2KB) (2KB) (2KB) Testing Plans After Fabrication Taped-out Layout for BRGTC1 The testing platform enables running small 2x2mm 1.3M transistors in IBM 130nm test programs on BRGTC1 to compare the RISC processor, 16KB SRAM performance and energy of pure-software kernels HLS-generated accelerators versus the HLS-generated sorting accelerator Static Timing Analysis Freq. @ 246 MHz Cornell University Christopher Torng 4 / 4