Enabling Realistic Fine-Grain Voltage Scaling with Reconfigurable - PowerPoint PPT Presentation

Enabling Realistic Fine-Grain Voltage Scaling with Reconfigurable Power Distribution Networks Waclaw Godycki, Christopher Torng, Ivan Bukreyev Alyssa Apsel, Christopher Batten School of Electrical and Computer Engineering Cornell University 47th Int’l Symp. on Microarchitecture, Dec 2014

• Motivation • FGVS Architecture: FG-SYNC+ FGVS Circuits: RPDN Methodology and Evaluation Motivation: Integrated Voltage Regulation (IVR) Key Benefit of IVR Discrete Off-Chip Voltage Regulators ◮ Reduced System Cost Integrated On-Chip Voltage Regulators Core 0 Core 1 Core 2 Core 3 On-Chip Interconnect Cache Cache Cache Cache Bank Bank Bank Bank Cornell University Christopher Torng 2 / 22

• Motivation • FGVS Architecture: FG-SYNC+ FGVS Circuits: RPDN Methodology and Evaluation Motivation: Integrated Voltage Regulation (IVR) Key Benefit of IVR Discrete Off-Chip Voltage Regulators ◮ Reduced System Cost Challenges of IVR Integrated On-Chip Voltage Regulators ◮ Integrated energy-storage elements have low energy densities ◮ Low switching speeds with high Core 0 Core 1 Core 2 Core 3 parasitic losses On-Chip Interconnect Cache Cache Cache Cache Bank Bank Bank Bank Cornell University Christopher Torng 2 / 22

• Motivation • FGVS Architecture: FG-SYNC+ FGVS Circuits: RPDN Methodology and Evaluation Motivation: Integrated Voltage Regulation (IVR) Key Benefit of IVR Discrete Off-Chip Voltage Regulators ◮ Reduced System Cost Challenges of IVR Integrated On-Chip Voltage Regulators ◮ Integrated energy-storage elements have low energy densities ◮ Low switching speeds with high Core 0 Core 1 Core 2 Core 3 parasitic losses A New Era of IVR On-Chip Interconnect ◮ Energy storage elements have Cache Cache Cache Cache slightly improved energy densities Bank Bank Bank Bank ◮ Faster switches with low parasitic losses Cornell University Christopher Torng 2 / 22

• Motivation • FGVS Architecture: FG-SYNC+ FGVS Circuits: RPDN Methodology and Evaluation Motivation: Integrated Voltage Regulation (IVR) Intel Haswell Discrete Figure from D. Kanter, MPR'13 Off-Chip Voltage Regulators V CCIN V CPU0 V DDQ DRAM Cntl V CPU1 CPUs … + Ring Interconnect Cache V LLC Integrated On-Chip V RING System FIVR Voltage Regulators Agent V GPU + Graphics PCIe … Engine + DMI V IOA Core 0 Core 1 Core 2 Core 3 V SA "Fully" Integrated Voltage Regulator (FIVR) On-Chip Interconnect Intel Haswell integrates the voltage control loop circuitry on-die Cache Cache Cache Cache with inductors in-package . Bank Bank Bank Bank Cornell University Christopher Torng 3 / 22

• Motivation • FGVS Architecture: FG-SYNC+ FGVS Circuits: RPDN Methodology and Evaluation Motivation: Integrated Voltage Regulation (IVR) Intel Haswell Discrete Figure from D. Kanter, MPR'13 Off-Chip Voltage Regulators V CPU0 V DDQ V CCIN DRAM Cntl V CPU1 CPUs … Ring Interconnect + Cache V LLC Integrated On-Chip System V RING FIVR Voltage Regulators Agent V GPU + Graphics PCIe … Engine + DMI V IOA Core 0 Core 1 Core 2 Core 3 V SA "Fully" Integrated Voltage Regulator (FIVR) On-Chip Interconnect Intel Haswell integrates the voltage control loop circuitry on-die Cache Cache Cache Cache with inductors in-package . Bank Bank Bank Bank Potential for Fine-Grain Voltage Scaling Cornell University Christopher Torng 3 / 22

• Motivation • FGVS Architecture: FG-SYNC+ FGVS Circuits: RPDN Methodology and Evaluation Motivation: Fine-Grain Voltage Scaling Opportunities Knuth-Morris-Pratt String Search 0 Cores 7 Breadth-First Search 0 Cores 7 Radix Sort 0 Cores 7 time Core Busy Core Waiting Cornell University Christopher Torng 4 / 22

• Motivation • FGVS Architecture: FG-SYNC+ FGVS Circuits: RPDN Methodology and Evaluation Motivation: Fine-Grain Voltage Scaling Opportunities Knuth-Morris-Pratt String Search 0 Cores 7 90 μ s Breadth-First Search 0 Cores 7 7 μ s Radix Sort 0 Cores 7 time 2.3 μ s Core Busy Core Waiting Cornell University Christopher Torng 4 / 22

• Motivation • FGVS Architecture: FG-SYNC+ FGVS Circuits: RPDN Methodology and Evaluation Enabling Realistic Fine-Grain Voltage Scaling Power Fine-Grain Distribution DVFS Network Controller Core 0 Core 1 Core 2 Core 3 On-Chip Interconnect Cache Cache Cache Cache Bank Bank Bank Bank Cornell University Christopher Torng 5 / 22

• Motivation • FGVS Architecture: FG-SYNC+ FGVS Circuits: RPDN Methodology and Evaluation Enabling Realistic Fine-Grain Voltage Scaling Power Fine-Grain Distribution DVFS Network Controller Stats Core 0 Core 1 Core 2 Core 3 On-Chip Interconnect Cache Cache Cache Cache Bank Bank Bank Bank Cornell University Christopher Torng 5 / 22

• Motivation • FGVS Architecture: FG-SYNC+ FGVS Circuits: RPDN Methodology and Evaluation Enabling Realistic Fine-Grain Voltage Scaling Power Power Fine-Grain Distribution DVFS Modes Network Controller Stats Core 0 Core 1 Core 2 Core 3 On-Chip Interconnect Cache Cache Cache Cache Bank Bank Bank Bank Cornell University Christopher Torng 5 / 22

• Motivation • FGVS Architecture: FG-SYNC+ FGVS Circuits: RPDN Methodology and Evaluation Enabling Realistic Fine-Grain Voltage Scaling Power Power Fine-Grain Distribution DVFS Modes Network Controller Voltages Stats Core 0 Core 1 Core 2 Core 3 On-Chip Interconnect Cache Cache Cache Cache Bank Bank Bank Bank Cornell University Christopher Torng 5 / 22

• Motivation • FGVS Architecture: FG-SYNC+ FGVS Circuits: RPDN Methodology and Evaluation Enabling Realistic Fine-Grain Voltage Scaling FGVS Architecture: FG-SYNC+ Power Power Use lightweight software hints and Distribution Modes FG-SYNC+ lookup tables derived offline to enable Network fast multi-level voltage configuration Voltages Stats Core 0 Core 1 Core 2 Core 3 On-Chip Interconnect Cache Cache Cache Cache Bank Bank Bank Bank Cornell University Christopher Torng 5 / 22

• Motivation • FGVS Architecture: FG-SYNC+ FGVS Circuits: RPDN Methodology and Evaluation Enabling Realistic Fine-Grain Voltage Scaling FGVS Architecture: FG-SYNC+ Power Use lightweight software hints and RPDN Modes FG-SYNC+ lookup tables derived offline to enable fast multi-level voltage configuration Voltages Stats FGVS Circuits: RPDN Core 0 Core 1 Core 2 Core 3 Enable sprinting cores to dynamically borrow energy storage from resting On-Chip Interconnect cores Cache Cache Cache Cache Bank Bank Bank Bank Cornell University Christopher Torng 5 / 22

• Motivation • FGVS Architecture: FG-SYNC+ FGVS Circuits: RPDN Methodology and Evaluation Enabling Realistic Fine-Grain Voltage Scaling FGVS Architecture: FG-SYNC+ Power Use lightweight software hints and RPDN Modes FG-SYNC+ lookup tables derived offline to enable fast multi-level voltage configuration Voltages Stats FGVS Circuits: RPDN Core 0 Core 1 Core 2 Core 3 Enable sprinting cores to dynamically borrow energy storage from resting On-Chip Interconnect cores Cache Cache Cache Cache Bank Bank Bank Bank Methodology and Evaluation Cornell University Christopher Torng 5 / 22

• Motivation • FGVS Architecture: FG-SYNC+ FGVS Circuits: RPDN Methodology and Evaluation Enabling Realistic Fine-Grain Voltage Scaling FGVS Architecture: FG-SYNC+ Power Use lightweight software hints and RPDN Modes FG-SYNC+ lookup tables derived offline to enable fast multi-level voltage configuration Voltages Stats FGVS Circuits: RPDN Core 0 Core 1 Core 2 Core 3 Enable sprinting cores to dynamically borrow energy storage from resting On-Chip Interconnect cores Cache Cache Cache Cache Bank Bank Bank Bank Methodology and Evaluation Architecture and Circuits Co-Design Approach Cornell University Christopher Torng 5 / 22

Motivation • FGVS Architecture: FG-SYNC+ • FGVS Circuits: RPDN Methodology and Evaluation Fine-Grain Synchronization Controller (FG-SYNC+) parallel_for(int i=0; i<N; n++){ Power Before Start: Work Left Hint Distribution FG-SYNC+ Network Loop Start: Activity Hint -- busy < loop body > Loop Ends: Activity Hint -- waiting Stats } Core 0 Core 1 Core 2 Core 3 On-Chip Interconnect Cache Cache Cache Cache Bank Bank Bank Bank Cornell University Christopher Torng 6 / 22

Motivation • FGVS Architecture: FG-SYNC+ • FGVS Circuits: RPDN Methodology and Evaluation Fine-Grain Synchronization Controller (FG-SYNC+) parallel_for(int i=0; i<N; n++){ Power Power Before Start: Work Left Hint Distribution Modes FG-SYNC+ Network Loop Start: Activity Hint -- busy < loop body > Loop Ends: Activity Hint -- waiting Stats } A A A A N N N N Core 0 Core 1 Core 2 Core 3 A A A w S N N r On-Chip Interconnect A A w w S S r r A w w w X r r r Cache Cache Cache Cache Activity Pattern DVFS Mode Pattern Bank Bank Bank Bank ( N, r Nominal, rest ) ( A ctive W aiting ) ( S, X Sprint modes ) Cornell University Christopher Torng 6 / 22