EECS 373 Im not Prabal Design of Microprocessor-Based Systems You - PDF document

Announcements EECS 373 • I’m not Prabal Design of Microprocessor-Based Systems – You probably noticed – He’s in Washington DC doing this and this – He regrets that he cannot be here today and will not have OH • We’re working on additional GSI/IA office hours (OH) Branden Ghena – Pat Pannuto 10-11am MW in EECS Learning Center University of Michigan • (Glass rooms between BBB and Dow) Lecture 5: Memory and Peripheral Buses January 22, 2015 1 2 Outline Accessing memory locations from C • Announcements • Memory has an address and value • Can equate a pointer to desired address • Accessing memory from Assembly/C • Can set/get de-referenced value to change memory • Busses: The glue that connects the pieces #define SYSREG_SOFT_RST_CR 0xE0042030 • ARM Advanced Peripheral Bus (APB) uint32_t *reg = (uint32_t *)(SYSREG_SOFT_RST_CR); main () { • ARM Advanced High-performance Bus Light (AHB-Lite) *reg |= 0x00004000; // Reset GPIO hardware *reg &= ~(0x00004000); } 3 4 What happens when this “ instruction ” executes? “ *reg += 3 ” is turned into a ld, add, str sequence • Load instruction – A bus read operation commences – The CPU drives the address “ reg ” onto the address bus #include <stdio.h> #include <inttypes.h> – The CPU indicated a read operation is in process (e.g. R/W#) – Some “ handshaking ” occurs #define REG_FOO 0x40000140 – The target drives the contents of “ reg ” onto the data lines – The contents of “ reg ” is loaded into a CPU register (e.g. r0) main () { • Add instruction uint32_t *reg = (uint32_t *)(REG_FOO); – An immediate add (e.g. add r0, #3) adds three to this value *reg += 3; • Store instruction – A bus write operation commences printf( “ 0x%x\n ” , *reg); // Prints out new value – The CPU drives the address “ reg ” onto the address bus } – The CPU indicated a write operation is in process (e.g. R/W#) – Some “ handshaking ” occurs – The CPU drives the contents of “ r0 ” onto the data lines – The target stores the data value into address “ reg ” 5 6

Some useful C keywords Outline • const • Announcements – Makes variable value or pointer parameter unmodifiable – const foo = 32; • Accessing memory from Assembly/C • register – Tells compiler to locate variables in a CPU register if possible • Busses: The glue that connects the pieces – register int x; • static • ARM Advanced Peripheral Bus (APB) – Preserve variable value after its scope ends – Does not go on the stack – static int x; • ARM Advanced High-performance Bus Light (AHB-Lite) • volatile – Opposite of const – Can be changed in the background – volatile int I; 7 8 Busses: the glue that connects the pieces Actel SmartFusion system/bus architecture C EECS 370 Assembly Central Machine Code Software ISA Processing Hardware Unit ldr (read) bl (int) str (write) System Buses AHB/APB Interrupts Internal & GPIO/INT Timers USART DAC/ADC External Memory Internal External 9 10 Why have so many busses? Advanced Microcontroller Bus Architecture (AMBA) - Advanced High-performance Bus (AHB) • Many designs considerations - Advanced Peripheral Bus (APB) – Master vs Slave – Internal vs External – Bridged vs Flat – Memory vs Peripheral – Synchronous vs Asynchronous – High-speed vs low-speed – Serial vs Parallel AHB APB – Single master vs multi master • High performance • Low power – Single layer vs multi layer • Pipelined operation • Latched address/control – Multiplexed A/D vs demultiplexed A/D • Burst transfers • Simple interface • Multiple bus masters • Suitable of many • Discussion: what are some of the tradeoffs? peripherals • Split transactions 11 12

Outline APB: a simple bus that is easy to work with • Announcements • Low-cost • Accessing memory from Assembly/C • Low-power • Busses: The glue that connects the pieces • Low-complexity • ARM Advanced Peripheral Bus (APB) • Low-bandwidth • ARM Advanced High-performance Bus Light (AHB-Lite) • Non-pipelined • Ideal for peripherals 13 14 Notation APB bus state machine • IDLE – Default APB state • SETUP – When transfer required – PSELx is asserted Setup phase begins with this rising edge – Only one cycle • ACCESS – PENABLE is asserted – Addr, write, select, and write data remain stable – Stay if PREADY = L – Goto IDLE if PREADY = H and no more data – Goto SETUP is PREADY = H and more data pending Setup Access Phase Phase 15 16 APB signal definitions APB bus signals in action • PCLK • PCLK: the bus clock source (rising-edge triggered) – Clock • PRESETn: the bus (and typically system) reset signal (active low) • PADDR • PADDR: the APB address bus (can be up to 32-bits wide) – Address on bus • PSELx: the select line for each slave device • PWRITE PENABLE: indicates the 2 nd and subsequent cycles of an APB xfer • – 1=Write, 0=Read • PWRITE: indicates transfer direction (Write=H, Read=L) • PWDATA: the write data bus (can be up to 32-bits wide) • PWDATA • PREADY: used to extend a transfer – Data written to the • PRDATA: the read data bus (can be up to 32-bits wide) I/O device. • PSLVERR: indicates a transfer error (OKAY=L, ERROR=H) Supplied by the bus master/processor. 17 18

APB bus signals A write transfer with no wait states • PSEL Setup phase begins – Asserted if the current with this rising edge bus transaction is targeted to this device • PENABLE – High during entire transaction other than the first cycle. • PREADY – Driven by target. Similar to our #ACK. Indicates if the target is ready to do transaction. Setup Access Phase Phase Each target has it ’ s own PREADY 19 20 A write transfer with wait states A read transfer with no wait states Setup phase begins Setup phase begins with this rising edge with this rising edge Setup Access Setup Wait Wait Access Phase Phase Phase State State Phase 21 22 A read transfer with wait states Example setup Setup phase begins • We will assume we have one bus master with this rising edge “CPU” and two slave devices (D1 and D2) – D1 is mapped to 0x00001000-0x0000100F – D2 is mapped to 0x00001010-0x0000101F Setup Wait Wait Access Phase State State Phase 23

CPU stores to location 0x00001004 with no stalls Writes Let’s do some hardware examples! D1 D2 25 26 Design a device which writes to a register whenever Reg A should be written at address 0x00001000 What if we want to have the LSB of this register any address in its range is written Reg B should be written at address 0x00001004 control an LED? PWDATA[31:0] PREADY PWDATA[31:0] PREADY 32-bit Reg A D[31:0] PWRITE PWRITE Q[31:0] 32-bit Reg EN PENABLE D[31:0] PENABLE C Q[31:0] EN PSEL PSEL LED C PADDR[7:0] PADDR[7:0] 32-bit Reg B D[31:0] Q[31:0] PCLK PCLK EN C We ¡are ¡assuming ¡APB ¡only ¡gets ¡lowest ¡8 ¡bits ¡of ¡address ¡here… We ¡are ¡assuming ¡APB ¡only ¡gets ¡lowest ¡8 ¡bits ¡of ¡address ¡here… 27 28 Let’s say we want a device that provides data from Reads… a switch on a read to any address it is assigned. (so returns a 0 or 1) PREADY PRDATA[32:0] PWRITE PENABLE Mr. Switch PSEL PADDR[7:0] PCLK The key thing here is that each slave device has its own read data (PRDATA) bus! Recall ¡that ¡“R” ¡is ¡from ¡the ¡initiator’s ¡viewpoint— the device drives data when read. 29 30

Device provides data from switch A if address All reads read from register, all writes write… 0x00001000 is read from. B if address 0x00001004 is read from PREADY PWDATA[31:0] PREADY PRDATA[31:0] PRDATA[31:0] PWRITE PWRITE 32-bit Reg PENABLE PENABLE D[31:0] Mr. Q[31:0] EN Switch PSEL PSEL C Mrs. PADDR[7:0] Switch PADDR[7:0] PCLK PCLK PREADY We ¡are ¡assuming ¡APB ¡only ¡gets ¡lowest ¡8 ¡bits ¡of ¡address ¡here… 31 32 Things left out… Verilog! • There is another signal, PSLVERR (APB Slave Error) which we can drive high if things go bad. /*** APB3 BUS INTERFACE ***/ input PCLK, // clock – We’ll just tie that to 0. input PRESERN, // system reset input PSEL, // peripheral select input PENABLE, // distinguishes access phase • PRESETn output wire PREADY, // peripheral ready signal output wire PSLVERR, // error signal – Active low system reset signal input PWRITE, // distinguishes read and write cycles input [31:0] PADDR, // I/O address – (needed for stateful peripherals) input wire [31:0] PWDATA, // data from processor to I/O device (32 bits) output reg [31:0] PRDATA, // data to processor from I/O device (32-bits) /*** I/O PORTS DECLARATION ***/ • Note that we are assuming that our device need output reg LEDOUT, // port to LED not stall. input SW // port to switch ); – We could stall if needed. assign PSLVERR = 0; • I can’t find a limit on how long, but I suspect at assign PREADY = 1; some point the processor would generate an error. 33 34 Outline AHB-Lite supports single bus master and provides high-bandwidth operation • Announcements • Burst transfers • Accessing memory from Assembly/C • Single clock-edge operation • Busses: The glue that connects the pieces • Non-tri-state • ARM Advanced Peripheral Bus (APB) implementation • ARM Advanced High-performance Bus Light (AHB-Lite) • Configurable bus width 35 36