EE 457 Unit 7d Virtual Memory 2 Virtual Memory Concept A - PowerPoint PPT Presentation

1 EE 457 Unit 7d Virtual Memory

2 Virtual Memory Concept • A mechanism for hiding the details of how much physical memory exists and how it’s being shared • Allows the OS to – Efficiently share the physical memory between several running programs/processes and provide protection against each other – Remove the need of the programmer to know how much memory is physically present and/or give the illusion of more or less physical memory than is present • Use MM as a cache for multiple programs and their data as they run using secondary storage (hard-drive) as the home location

3 Memory Hierarchy & Caching • Lower levels act as a cache for upper levels Registers L1 Cache ~ 1ns L1/L2 is a “cache” for L2 Cache main memory ~ 10ns Main Memory Virtual memory ~ 100 ns provides each Disk / Secondary Storage process its own ~1-10 ms address space in secondary storage and uses main memory as a cache

4 Virtual Memory Motivation • Virtual memory is largely discussed in operating systems courses – We will focus on HW support for VM • Magnetic hard drive consists of – Double sided surfaces/platters (with R/W head) – Each platter is divided into concentric tracks of small sectors that each store several thousand bits Read/Write Head 0 • Seek Time: Time needed to 3-12 ms Read/Write Head 1 position the read-head above Surfaces … the proper track • Rotational delay: Time needed 5-6 ms Read/Write Head 7 to bring the right sector under Sector 0 the read-head • Depends on rotation Track 0 Sector 1 speed (e.g. 5400 RPM) Track 1 • Transfer Time: 0.1 ms • Disk Controller Overhead: + 2.0 ms ~20 ms Sector 2

5 Address Spaces • Physical address spaces corresponds to the actual system address range Program/Process 1,2,3,… (based on the width of the address bus) of the processor and how much 0xffff ffff 0xffff ffff - Not main memory is physically present Mapped used I/O • Each process/program runs in its own - 0xbfffffff private "virtual" address space 0xc0000000 I/O Stack – Virtual address space can be larger 0x80000000 - (or smaller) than physical memory Heap Not – Virtual address spaces are protected used - from each other Data 0x10000000 0x3fffffff - Mem. Code 0x00000000 0x00000000 32-bit Physical 32-bit Fictitious Virtual Address Space w/ Address Spaces only 1 GB of Mem ( > 1GB Mem)

6 Processes Program/Process • Process 1,2,3,… – (def 1.) Address Space + Threads 0xffff ffff - • (Virtual) Address Space = Protected view of memory Mapped • 1 or more threads I/O – (def 2.) : Running instance of a program that has - limited rights 0xc0000000 Stack • Memory is protected: Address translation (VM) ensures no - access to any other processes' memory Heap • I/O is protected: Processes execute in user-mode (not kernel mode) which generally means direct I/O access is - disallowed instead requiring system calls into the kernel Data 0x10000000 • - OS Kernel is not considered a "process" = Thread – Has access to all resources and much of its code is Code 0x00000000 invoked under the execution of a user process thread Address Spaces

7 Virtual Address Spaces (VAS) • Virtual address spaces 0 - Code Program/Process 1 - Code 1,2,3,… (VASs) are broken into 0 - Code 2 - Data 1 - Code blocks called "pages" 3 - Stack 0xffff ffff - 2 - Data 4 - Heap Mapped 3 - Stack • Depending on the … I/O 4 - Heap - program, much of the 0 0 0xc0000000 Stack 1 1 virtual address space will 2 - 2 3 be unused 3 Heap 0 Unalloc • Pages can be allocated - 1 … Data 2 0x10000000 "on demand" (i.e. when - 0 the stack grows, etc.) 1 Code 0x00000000 2 • All allocated pages can be Unalloc Unalloc stored in secondary … storage (hard drive) Secondary Used/Unused Blocks in Storage Virtual Address Space

8 Physical Address Space (PAS) • Physical memory is broken into 0 - Code 1 - Code page-size blocks called "frames" 0 - Code 2 - Data • 0xffffffff 1 - Code Multiple programs can be running 3 - Stack I/O 2 - Data and 4 - Heap and their pages can share the 3 - Stack un- … physical memory used 4 - Heap area 0 • Physical memory acts as a cache 0 0x3fffffff 1 frame 1 for pages with secondary storage 2 0-Code 2 acting as the backing store (next 3 Pg. 0 3 0 lower level in the hierarchy) Pg. 2 Unalloc 1 … 2-Data • A page can be: 2 Pg. 0 – 0 Unallocated (not needed frame 0x00000000 1 yet…stack/heap) 2 – Allocated and residing in secondary Unalloc 1GB Physical storage ( Uncached ) Unalloc Memory and Secondary – Allocated and residing in main … 32-bit Address Storage memory ( Cached ) Space Fictitious Virtual Address Spaces

9 Paging Phys. Addr. Space • Virtual address space is divided into equal 0xffffffff size "pages" (often around 4KB) I/O and • Physical memory is broken into page un- used frames (which can hold any page of virtual area memory and then be swapped for another 0x3fffffff frame page) 0-Code Pg. 0 • Virtual address spaces can be contiguous Pg. 2 while physical layout is not 2-Data Pg. 0 Physical Frame of frame 0x00000000 memory can hold data from any virtual page. Since all pages are the Pg. 0 Pg. 0 same size any page can Pg. 1 Pg. 1 go in any frame (and be Pg. 2 Pg. 2 swapped at our desire). Pg. 3 unused unused unused … … Proc. 1 VAS Proc. 2 VAS

10 Virtual vs. Physical Addresses 0 - Code VA: 0x040000 1 - Code VA: 0x100080 2 - Data • Key : Programs are written using virtual 0xffffffff I/O 3 - Stack 0 - Code addresses and 4 - Heap 1 - Code un- • HW & the OS will translate the virtual … 2 - Data used addresses used by the program to the 3 - Stack area 0 4 - Heap physical address where that page resides PA:0x3fffffff frame 1 0 • If an attempt is made to access a page 0-Code PA: 0x21b000 2 1 Pg. 0 that is not in physical memory, HW 3 2 Pg. 2 Unalloc generates a "page fault exception" and 3 2-Data … PA: 0x11f000 0 the OS is invoked to bring in the page to Pg. 0 1 physical memory (possibly evicting 0 2 another page) frame PA: 0x0 1 • 2 Notice: Virtual addresses are not unique Physical Unalloc – Each program/process has VA: 0x00000000 Memory and Unalloc Secondary Address Space … Storage Virtual Physical Translation Unit / Fictitious Virtual Addr Proc. Addr MMU Memory Address Spaces Core PA: 0x21b000 VA: 0x040000 (Mem. Mgmt. Unit) Data

11 Summary 0 - Code VA: 0x040000 • Program takes an abstract (virtual) view of 1 - Code memory and uses virtual addresses and VA: 0x100080 2 - Data 0xffffffff necessary data is broken into large chunks I/O 3 - Stack 0 - Code and 4 - Heap called pages 1 - Code un- … 2 - Data • used HW and OS work together to bring pages into 3 - Stack area main memory acting as a cache and allowing 0 4 - Heap PA:0x3fffffff frame sharing 1 0 0-Code PA: 0x21b000 2 1 • HW and OS work together to perform Pg. 0 3 2 translation between: Pg. 2 Unalloc 3 2-Data – … Virtual address : Address used by the process PA: 0x11f000 0 Pg. 0 (programmer) 1 0 2 – Physical address : Physical memory location of frame PA: 0x0 1 the desired data 2 • Translation allows protection against other Physical Unalloc Memory and programs Unalloc Secondary Address Space … Storage Virtual Physical Translation Unit / Fictitious Virtual Addr Proc. Addr MMU Memory Address Spaces Core (Mem. Mgmt. Unit) Data

12 VM Design Implications • SLOW secondary storage access on page faults (10 ms) – Implies page size should be fairly large (i.e. once we’ve taken the time to find data on disk, make it worthwhile by accessing a reasonably large amount of data) – Implies the placement of pages in main memory should be fully associative to reduce conflicts and maximize page hit rates – Implies a "page fault" is going to take so much time to even access the data that we can handle them in software (via an exception) rather than using HW like typical cache misses – Implies eviction algorithms like LRU can be used since reducing page miss rates will pay off greatly – Implies write-back (write-through would be too expensive)

13 Page Tables ADDRESS TRANSLATION

14 Page Size and Address Translation • Since pages are usually retrieved from disk, we size them to be fairly large (several KB) to amortize the large access time • Virtual page number to physical page frame translation performed by HW unit = MMU (Mem. Management Unit) • Page table is an in-memory data structure that the HW MMU will use to look up translations from VPN to PPFN 31 12 11 0 Virtual Address Virtual Page Number Offset within page 0 0 0 0 2 0 0 0 20 12 Translation Copied Lookup VPN 0x00040 Process to it lives in PPFN: 0x0021b (MMU + Page Table) 18 31 30 12 11 0 29 Phys. Page Frame Physical Address 00 Offset within page Number 0 0 2 1 b 0 0 0