ECE 550D Fundamentals of Computer Systems and Engineering Fall 2016 Storage and Clocking Tyler Bletsch Duke University Slides are derived from work by Andrew Hilton (Duke)
VHDL: Behavioral vs Structural • A few words about VHDL • Structural: • Spell out at (roughly) gate level • Abstract piece into entities for abstraction/re-use • Very easy to understand what synthesis does to it • Behavioral: • Spell out at higher level • Sequential statements, for loops, process blocks • Can be difficult to understand how it synthesizes • Difficult to resolve performance issues 2
Last time… • Who can remind us what we did last time? • Add • Substract • Bit shift • Floating point 3
So far… • We can make logic to compute “math” • Add, subtract,… (we’ll see multiply/divide later) • Bitwise: AND, OR, NOT,… • Shifts • Selection (MUX) • …pretty much anything • But processors need state (hold value) • Registers • … 4
Memory Elements • All the circuits we looked at so far are combinational circuits: the output is a Boolean function of the inputs. • We need circuits that can remember values (registers, memory) • The output of the circuit is a function of the input and a function of a stored value (state) • Circuits with storage are called sequential circuits • Key to storage: feedback loops from outputs to inputs 5
Ideal Storage – Where We’re Headed • Ultimately, we want something that can hold 1 bit and we want to control when it is re-written “flip flop” = bit to be written device that bit currently being held holds one bit to control bit (0 or 1) when we write • However, instead of just giving it to you as a magic black box, we’re going to first dig a bit into the box 6
Building up to the D Flip-Flop and beyond D Q D Q R R D Q E D Q Q D Q D D D DFF Q Q Q Q D D DFF DFF latch latch DFF E E !Q DFF !Q E Q E Q C E Q Q E Q S Q E Q D S D Q D Q D Q D DFF 32 bit reg latch E E Q Q E Q SR Latch D Latch D Flip-Flop Register 7 (too awkward) (bad timing) (okay but only one bit) ( nice! )
FF Step #1: NOR-based Set-Reset (SR) Latch 0 0 R R 0 1 1 Q Q 0 0 1 1 0 0 Q Q 0 S S R S Q 0 0 Q 0 1 1 1 0 0 1 1 - Don’t set both S & R to 1. Seriously, don’t do it. 8
Set-Reset Latch (Continued) 0 0 R R 0 1 1 Q Q 0 0 1 1 0 0 Q Q 1 S S Time 1 S 0 1 R 0 1 Q 0 9
Set-Reset Latch (Continued) 0 0 R R 0 1 1 Q Q 0 0 1 1 0 0 Q Q 1 S S Time 1 S 0 Set Signal Goes High 1 R 0 1 Q 0 Output Signal Goes High 10
Set-Reset Latch (Continued) 0 0 R R 0 1 1 Q Q 0 0 1 1 0 0 Q Q 1 S S Time 1 S 0 Set Signal Goes Low 1 R 0 1 Q 0 Output Signal Stays High 11
Set-Reset Latch (Continued) 0 0 R R 0 1 1 Q Q 0 0 1 1 0 0 Q Q 1 S S Time 1 S 0 Until Reset Signal 1 R Goes High 0 1 Q 0 Then Output Signal Goes Low 12
SR Latch • Downside: S and R at once = chaos • Downside: Bad interface • So let’s build on it to do better 13
Building up to the D Flip-Flop and beyond D Q D Q R R D Q E D Q Q D Q D D D DFF Q Q Q Q D D DFF DFF latch latch DFF E E !Q DFF !Q E Q E Q C E Q Q E Q S Q E Q D S D Q D Q D Q D DFF 32 bit reg latch E E Q Q E Q SR Latch D Latch D Flip-Flop Register 14 (too awkward) (bad timing) (okay but only one bit) ( nice! )
FF Step #2: Data Latch (“D Latch”) R Q Q S Starting with SR Latch 15
Data Latch (D Latch) R E nable Q Q D ata S Starting with SR Latch Change interface to Data + Enable (D + E) If E=0, then R=S=0. If E=1, then S=D and R=!D 16
Data Latch (D Latch) R E nable D E Q Q 0 1 0 1 1 1 - 0 Q Q D ata S Time 1 D 0 E goes high 1 E 0 D “latched” 1 Q Stays as output 0 17
Data Latch (D Latch) R E nable D E Q Q 0 1 0 1 1 1 - 0 Q Q D ata S Time Does not affect Output 1 D 0 E goes low 1 E 0 Output unchanged 1 Q By changes to D 0 18
Data Latch (D Latch) R E nable D E Q Q 0 1 0 1 1 1 - 0 Q Q D ata S Time 1 D 0 E goes high 1 E 0 D “latched” 1 Q Becomes new output 0 19
Data Latch (D Latch) R E nable D E Q Q 0 1 0 1 1 1 - 0 Q Q D ata S Time 1 D 0 Slight Delay 1 E 0 (Logic gates take time) 1 Q 0 20
Logic Takes Time • Logic takes time: • Gate delays: delay to switch each gate • Wire delays: delay for signal to travel down wire • Other factors (not going into them here) • Need to make sure that signals timing is right • Don’t want to have races or wacky conditions.. 21
Clocks • Processors have a clock: • Alternates 0 1 0 1 • Like the processor’s internal metronome • Latch logic latch in one clock cycle One clock cycle • 3.4 GHz processor = 3.4 Billion clock cycles/sec 22
FF Step #3: Using Level-Triggered D Latches • First thoughts: Level Triggered • Latch enabled when clock is high • Hold value when clock is low D Q D Q D Logic D 3 3 latch latch E Q E Q Clk This slide describes how D-latches can malfunction because they were level triggered. 23 Real D-flip-flops are edge-triggered , and we’re showing you why that’s important.
Strawman: Level Triggered • How we’d like this to work • Clock is low, all values stable Clk 100 001 010 111 D Q D Q D Logic D 3 3 latch latch E Q E Q 0 Clk This slide describes how D-latches can malfunction because they were level triggered. 24 Real D-flip-flops are edge-triggered , and we’re showing you why that’s important.
Strawman: Level Triggered • How we’d like this to work • Clock goes high, latches capture and xmit new val Clk 100 100 010 010 D Q D Q D Logic D 3 3 latch latch E Q E Q 0 Clk This slide describes how D-latches can malfunction because they were level triggered. 25 Real D-flip-flops are edge-triggered , and we’re showing you why that’s important.
Strawman: Level Triggered • How we’d like this to work • Signals work their way through logic w/ high clk Clk 100 100 010 010 D Q D Q D Logic D 3 3 latch latch E Q E Q 0 Clk This slide describes how D-latches can malfunction because they were level triggered. 26 Real D-flip-flops are edge-triggered , and we’re showing you why that’s important.
Strawman: Level Triggered • How we’d like this to work • Clock goes low before signals reach next latch Clk 100 100 010 010 D Q D Q D Logic D 3 3 latch latch E Q E Q 0 Clk This slide describes how D-latches can malfunction because they were level triggered. 27 Real D-flip-flops are edge-triggered , and we’re showing you why that’s important.
Strawman: Level Triggered • How we’d like this to work • Clock goes low before signals reach next latch Clk 000 100 111 010 D Q D Q D Logic D 3 3 latch latch E Q E Q 0 Clk This slide describes how D-latches can malfunction because they were level triggered. 28 Real D-flip-flops are edge-triggered , and we’re showing you why that’s important.
Strawman: Level Triggered • How we’d like this to work • Everything stable before clk goes high Clk 000 100 111 010 D Q D Q D Logic D 3 3 latch latch E Q E Q 0 Clk This slide describes how D-latches can malfunction because they were level triggered. 29 Real D-flip-flops are edge-triggered , and we’re showing you why that’s important.
Strawman: Level Triggered • How we’d like this to work • Clk goes high again, repeat Clk 000 000 111 111 D Q D Q D Logic D 3 3 latch latch E Q E Q 0 Clk This slide describes how D-latches can malfunction because they were level triggered. 30 Real D-flip-flops are edge-triggered , and we’re showing you why that’s important.
Strawman: Level Triggered • Problem: What if signal reaches latch too early? • I.e., while clk is still high Clk 101 000 111 111 D Q D Q D Logic D 3 3 latch latch E Q E Q 0 Clk This slide describes how D-latches can malfunction because they were level triggered. 31 Real D-flip-flops are edge-triggered , and we’re showing you why that’s important.
Strawman: Level Triggered • Problem: What if signal reaches latch too early? • Signal goes right through latch, into next stage.. Clk 101 101 111 111 D Q D Q D Logic D 3 3 latch latch E Q E Q 0 Clk This slide describes how D-latches can malfunction because they were level triggered. 32 Real D-flip-flops are edge-triggered , and we’re showing you why that’s important.
That would be bad… • Getting into a stage too early is bad • Something else is going on there corrupted • Also may be a loop with one latch • Consider incrementing counter (or PC) • Too fast: increment twice? Eeek … 001 +1 D Q D latch E Q 010 3 This slide describes how D-latches can malfunction because they were level triggered. 33 Real D-flip-flops are edge-triggered , and we’re showing you why that’s important.
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