Early Prediction of Product Performance and Yield Via Technology - PowerPoint PPT Presentation

Early Prediction of Product Performance and Yield Via Technology Benchmark Choongyeun Cho 1 , Daeik D. Kim 1 , Jonghae Kim 2 , Daihyun Lim 1 , Sangyeun Cho 3 1 IBM, 2 Qualcomm, 3 U. Pittsburgh

Background • Process variation as grave concern: – Limits IC product performance and yield – Difficult to model / predict before tape-out • Product circuit is tested and qualified usually after BEOL process is complete – Test for final product is often expensive in terms of cost, time and resource 2

Background • Typical schedule for CMOS technology development and testing: Chip-level test Wk 24 t N BEOL Far- Wafer-level test Wk 20 t N-1 Si CMOS Technology Processing 8X Time Time Step Step Level Level Test Test (Week) (Week) Function block test Wk 17 t 7 BEOL 4X t N t N C4 C4 24 24 Chip Chip Circuit test Wk 15 t N-1 t N-1 M top M top 20 20 Wafer Wafer t 5 2X t 5 t 5 M 5 M 5 15 15 Block Block 1X t 2 t 1 t 1 M 1 M 1 12 12 Inline Inline Inline benchmark test Wk 12 t 1 CA FEOL Wk 10 FEOL PC t 0 SiO 2 Si t 0 t 0 FEOL FEOL 10 10 - - BOX Substrate Wk 0 3

Motivation • Use existing M1 data to predict product performance / yield – Device characterization is available early in manufacturing, typically at M1 level – M1 test data, if prudently selected, carries relevant information to reliably predict product performance and yield 4

Motivation Conventional Conventional Conventional Conventional Yield Yield Yield Yield Yield Yield Yield Yield Yield Yield This Work This work This work This work Circuit Circuit Circuit Circuit Circuit Circuit Circuit Circuit Circuit Circuit Model Model Model Model Model Model Calibration Calibration Bench- Bench- Bench- Bench- Bench- Bench- Bench- Bench- Mark Mark Mark Mark Mark Mark Mark Mark Tests Tests Tests Tests Tests Tests Tests Tests FEOL+M1 FEOL+M1 BEOL BEOL FEOL+M1 FEOL+M1 BEOL BEOL FEOL+M1 FEOL+M1 BEOL BEOL FEOL+M1 FEOL+M1 BEOL BEOL Process Process Process Process Process Process Process Process Process Process Process Process Process Process Process Process Time Time Time Time • Will reduce test cost and time for product circuit performance / yield 5

Methodology Well-chosen M1 data captures key M1 Data M1 Data process variation mechanisms (Vth, Tox, Lpoly, etc) m m Remove outlier and statistically Data filtering Data filtering unimportant parameters n n Predictor Predictor Use projected principal Feature Feature component to extract features extraction extraction while preserving most information p p relevant circuit parameters Nonlinear Nonlinear Neural net is employed to estimator estimator estimate product performance or yield 1 1 6 Product Parametric Product Parametric

Training and Testing Predictor Predictor Predictor Predictor Testing Testing Training Training M1 data M1 data M1 data M1 data Predictor Predictor 65nm SOI Testing Testing technology used Predictor Predictor for validation Estimated Estimated Training Training + + (12 wafers) Product Product - - Parameter Parameter Product Product Parameter Parameter Product Product parameter parameter Error Error 7

Experiment: 65nm SOI • M1 data set as an input: # of # of M1 test structure parameters parameters category (before (after screening) screening) FET 1,988 759 RO 248 83 SRAM 398 159 Capacitance 222 108 Total 2,856 1,109 • 10 wafers used for training, 2 wafers used for testing 8

Validation Circuit • Two product circuits 31mm 31mm chosen for validation Inverter Inverter Logic Logic of proposed method 1. Freq. divider as PLL EN EN EN EN component: self-osc Ring oscillator Ring oscillator 25mm 25mm freq. is estimated MIBS MIBS MIBS MIBS 2. Ring oscillator as logic product: gate DFF DFF DFF DFF delay of 101-stage CML CML RF divider RF divider PLL PLL inverter-based RO is predicted 9

Prediction Results Estimated Neural Net Mean Std dev parameter %err Freq divider Self-osc freq. 34.6GHz 2.9GHz (8.3%) 4.6% Idd 24.0mA 3.6mA (15.1%) 10.0% Yield 27.5% - 17.7% Delay 4.3ps 0.37ps (8.7%) 3.5% Ring Osc I A,RO 2.5mA 0.28mA (11.1%) 5.1% Yield 25.6% - 13.1% 10

Prediction Results 25 Linear fit Quadratic fit 20 Neural network Prediction error (%) 15 10 5 0 Self-osc Freq Idd Yield Delay I_A Yield • Neural net is slightly more accurate than linear estimator • Error comes mainly from: (1) BEOL variation and (2) Intra-die variation 11

Prediction Robustness • To evaluate the estimation robustness, training and Training Testing %err set set testing data sets are divided to slow and fast, and prediction was Slow Slow 4.5% performed • The prediction error does Slow Fast 5.6% not strongly depend on any particular combination of Fast Slow 5.5% training / testing data sets Fast Fast 4.9% • The proposed method is robust even when wafer variation is significant 12

Feedback to Design / Tech • Mapping from M1 measurement to product performance metric: – For technology, it reveals what device characteristics are most sensitive to product, and to what degree – Designer can make educated trade-off between design parameters – E.g. RO gate delay is related to tech parameters: τ ∝ + + I 0 . 817 I 0 . 765 V on off th (each parameter normalized) 13

Conclusion • Proposed an efficient statistical method to predict circuit performance and yield solely based on technology benchmark data available at M1 – <5% error for estimating mmWave freq. divider performance – <4% error for RO gate delay • This method significantly cuts time and cost of final product test 14