driven ECO Subramanyam Sripada Song Chen Synopsys Inc. Mar 16, - PowerPoint PPT Presentation

Efficient Incremental Flow for signoff- driven ECO Subramanyam Sripada Song Chen Synopsys Inc. Mar 16, 2017

Agenda • Background • Motivation • Approach • Results

Design/Complexity Projections SoC Transistor Count Trend Scenario Growth at (Logic + SRAM) Advanced Nodes 10 27 3X Growth 9 24 2015-2020 8 Billion Transistors 7 15 15 6 12 11 10 5 9 7 4 5 3 2 65nm 40nm 28nm 20nm FinFET 1 Modes Corners 2013 2014 2015 2016 2017 2018 2019 2020 Source: ITRS 2013 Source: Synopsys Customer & Partner Data

Signoff-driven timing closure Implementation Timing-driven optimization for critical scenarios hierarchically Signoff-driven ECO Signoff-accurate, Place and Route physically-aware, all-scenario ECO

Implementation ECO vs Signoff ECO • Hierarchical vs Flat full-chip – Implementation ECO is usually done block-level and top-level whereas signoff ECO is typically performed flat but MIM-aware, physically-aware • Timing scenarios – Number of timing scenarios is signoff ECO is full combination of modes and corners • Constraints – Timing constraints can be different between implementation and signoff

Multiply Instantiated Modules • MIM is very common: – Implementation ECO typically honors MIM as it sees single context – Signoff ECO needs to provide options to honor MIM or break away to meet final timing • Flat analysis eliminates MIM pessimism

Motivation • How to perform signoff ECO with all timing scenarios on huge (several hundred million instance) designs with high accuracy, efficient runtime, computational resources? - Efficient incremental flow [this presentation] - Violation driven circuit reduction [next presentation]

Traditional signoff ECO Parasitic Signoff Place and STA/ECO Route, ECO extraction (full chip) (hierarchical) (hierarchical)

Previous Attempts • Previous Attempts: – All functionality in single process – Perform post-route-ECO with a signoff timer accuracy • Limited success due to flat analysis on huge designs – Additional final flat signoff run

Incremental signoff ECO Incremental Incremental Incremental parasitic signoff STA Place and 3 1 extraction and ECO Route (StarRC) (PrimeTime) (IC Compiler II) 2

Incremental signoff ECO • PrimeTime runs full chip signoff STA • For each iteration, 1. PrimeTime performs physical ECO on all scenarios • Provides ECO changelist for P&R for each block [2] 2. IC Compiler II performs incremental hierarchical P&R • Provides incremental hierarchical database to StarRC 3. StarRC performs incremental hierarchical parasitic extraction • Provides incremental SPEF to PrimeTime 4. PrimeTime performs incremental full chip signoff STA

Incremental signoff ECO • All communication is done via binary database – Ascii versions are available for advanced users and for mix-and-match – Incremental SPEF has asymmetric coupling • All communication ensures data integrity via signature mechanism

Results Number of Outliers > 1% of Design Outliers > 2ps endpoints capture clock period A 22142 39 0 B 5552 1 0 C 322364 0 0 D 401534 13 0 E 6240 2 0 F 2071132 26 0 3X performance improvement over full STA analysis

Summary • There is a great need for optimizing the signoff ECO process – With all scenarios, signoff constraints and full-chip • Proposed a fully incremental signoff ECO system – Presented approach and results – Results have improved quite a bit since the paper