DPM Upgrade status Fibre’ trays Firmware R&D DUNE DAQ Hardware Meeting 24 24 May2018 Babak Abi, DAQ meeting 1
DPM Upgrade, , curr rrent status • DPM (RCE already proven performance in 35t & ProtoDUNE): Component Cost(£) • Xilinx Zynq Ultrascale FPGA ( xczu15 eg_ffvb1156) + 16GB DDR4-2666 Memory FPGA 2000 • Resource per APA: RAM 320 • ~3m System Logic Cells, 16xCPU (ARM A53)+8xARM(R5), 96xGTH 16.3Gb/s PCB 200 • SSD on M.2 Next Generation Form Factor (NGFF) Connector Assembly 250 • 18 Layer PCB, 110mm by 88mm approx , Designed to fit SLAC COB Other 200 • 10s pre-trigger buffer + 10minutes Post-trigger buffer components • Plan& schedule : 25 April 2018: plan in progress as scheduled Cost per DPM 2970(£) (price for 6 ) 1. System design and schematics, already done(SLAC&Oxford) 2. PCB layout – (High speed & dense PCB) Status : (Peter Hastings) 25 April 2018 ( final review end of June 2018 ) PCB layout (DDR4 and 10Gb lanes) in progress. Planning for test stand and test firmware (in 3. Signal integrity check (DDR4 and 10Gb/S+ ) progress). 4. Prototyping (September 2018) Placed order for DDR4 chips, need to place order a) PCB manufacturing x for FPGA ( long lead time we will receive the b) Components ordering (long lead time ) DDR4 chips 1 st August 2018 ) c) Assembly 5. Firmware and tests (SLAC + Oxford + ?…) • Oct 2018, firmware developer are very welcome Babak Abi, DAQ meeting 2
DPM Upgrade status • SLAC/OXFORD Board layout design – (Peter Hastings, 25 April 2018 ) Oxford DPM Single Zynq Ultrascale+ PCB Design Peter Hastings 24 May 2018 PCB stack has been change and whole board re-routed again Babak Abi, DAQ meeting 3
DPM status and schedule • Layout Produced Using Mentor Graphics Xpedition VX.2.3 Peter Hastings • Board stack up implemented giving greater control 24 May 2018 of impedances on certain traces (DDR4/Gigabit signalling) for both differential and single ended traces. Now at the stage of simulating and tuning nets to meet compliance for fast signals. • Stack up developed in unison with Express Circuits Group to ensure a UK based PCB manufacturer can actually build the design. • High Speed traces are being compliance checked using Hyperlynx VX.2.3 • This is still a work in progress but we aim to make the PCIE Gen 2 lines compliant with Gen 3 standards. All DPM signals are 10GBit Ethernet compliant. We will be using this tool to check DDR4 routing. • Still in schedule, • The PCB will be ready for review first week of June. Babak Abi, DAQ meeting 4
Quick estimation for • Quick look/estimation fibers trays or duct between CUC and cavern • Size and weight (per meter) • Do we have patch panels ? • Do we have safe environment to use non-armoured cable ? • Do we need to follow any Mine Safety Certification or standard? • Like MGTSV Mining Flame-retardant CUC Patch panel Patch panel We only estimate the size and weight that trays have to handle between CUC and cavern. Servers ( no talk about Inside the cavern or CUC room ) There might be more cables, like CAT6! and other 150 APA subsystems like timing PDS …. Babak Abi, DAQ meeting 5
Assuming we do have patch panel • so can use 144 fibre cable: The usual Weights of Rectangular size Rate Gbps # Links/APA #Link/10kt #Cable/10kt Weight Kg/m cm LSZH cables are half of 1.25 80 12000 84 59 25 this, this is example of 2.5 40 6000 42 30 18 5 20 3000 21 15 13 the heaviest cables 10 10 1500 11 8 9 • MGTSV class: Mining Fiber Optical Cable Used in Harsh Environment • With flame retardant and rodent resistance property, it is suitable for coal, gold, iron ore and other mines applications. Rectangular size Weight Kg/m cm 27 19 14 13 7 10 4 7 Babak Abi, DAQ meeting 6
Assuming we do not have patch panel • so can use 12 fibre cable LSZH : Rectangular size Rate Gbps # Links/APA #Link/10kt #Cable/10kt Weight Kg/m cm 1.25 80 12000 1000 38 19 2.5 40 6000 500 19 14 5 20 3000 250 10 10 10 10 1500 125 5 7 • MGTSV class 12 The armoured cable might have weight issue in case of 12 fiber/cable Rectangular Weight Kg/m size cm 150 38 75 27 38 19 19 14 Babak Abi, DAQ meeting 7
DPM (F (FPGA fir firmware) High-level data flow diagram https://docs.google.com/document/d/1prjeq0AiturRpx4egD7BXm_yLSNxE5V4j rxhf0XAq6U/edit?usp=sharing Babak Abi, DAQ meeting 8
DPM / FPGA fir firmware R&D • High-level data flow diagram for an FPGA based Sub Projects How much Wher exist already e system 1-CORE PS/PL Ryan/Larry • To go to more detail we need to answer some more 2-Compression PL J.J. 3-TPC Interface PL ? questions like : 4-Data Splitter PL ? • What is the trigger primitive parameters to be send out? 5-Filter PL Roy, Babak, Peter 6-Hit Finder PL J.J. • Additional block diagrams like bad channels masking ? Or 7-10GE(TCP) In core PL/PS ? data treatment 8- Buffer controller - PL/PS ? • ………… DDR4 9- Buffer controller - PS Roy, Babak, Peter SSD 10-GE(serial FELIX) PL ? Need people for firmware -> 11- PS C++ PS ? Time/Trigger Block PL Bristol + ? Babak Abi, DAQ meeting 9
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