The System Level Informal Specification, Requirements Functional Modeling Simulation Formal Arch. Selection System model Verification System Mapping architecture Scheduling Estimation Mapped and τ 1 τ 2 µ p1 scheduled model Simulation Formal Verification τ 3 τ 6 τ 5 τ 7 µ p2 Softw. model Hardw. model Simulation τ 8 τ 4 ASIC Softw. Generation Hardw. Synthesis bus m 1-3 m 2-4 m 7-8 Softw. blocks Hardw. blocks Simulation Prototype Fabrication Distributed Systems for Real-Time Applications: Analysis and Synthesis 24 Petru Eles May 2003
The System Level Informal Specification, Requirements Functional Modeling Simulation Formal Arch. Selection System model Verification System Mapping architecture Estimation Scheduling No No Mapped and scheduled model Simulation Formal Verification τ 1 Functionality OK? & Timing Softw. model Hardw. model Simulation τ 2 τ 3 Yes Softw. Generation Hardw. Synthesis τ 5 τ 6 Verification Softw. blocks Hardw. blocks Simulation engine τ 4 τ 7 No Prototype τ 8 Fabrication Distributed Systems for Real-Time Applications: Analysis and Synthesis 25 Petru Eles May 2003
The System Level Informal Specification, Requirements --------------- --------------- --------------- --------------- VHDL C++ --------------- --------------- Functional Modeling --------------- --------------- Simulation --------------- --------------- Formal Arch. Selection System model Verification System Mapping architecture Compiler& VHDL Estimation Scheduling ISA model Simulator Mapped and scheduled model Simulation Co-simulation engine Formal Verification N o t O K Softw. model Hardw. model Simulation Softw. Generation Hardw. Synthesis Softw. blocks Hardw. blocks Simulation Prototype Fabrication Distributed Systems for Real-Time Applications: Analysis and Synthesis 26 Petru Eles May 2003
System Level Design Flow Informal Specification, Requirements Functional Modeling Simulation Formal System model Arch. Selection Verification System Mapping architecture Scheduling Estimation not OK not OK Mapped and scheduled model Simulation Formal OK Verification not OK Softw. model Hardw. model Simulation Softw. Generation Hardw. Synthesis Softw. blocks Hardw. blocks Simulation Prototype Fabrication Distributed Systems for Real-Time Applications: Analysis and Synthesis 27 Petru Eles May 2003
System-level Design ☞ System-level design is performed before any effective hardware/software implementation has been generated. It is a design loop including the exploration of different ■ - architectures (including communication infrastructure) - mappings - schedules It is supported by ■ - system level models - estimation - analysis & formal verification - simulation Distributed Systems for Real-Time Applications: Analysis and Synthesis 28 Petru Eles May 2003
System-level Design ☞ System-level design is performed before any effective hardware/software implementation has been generated. It is a design loop including the exploration of different ■ - architectures (including communication infrastructure) - mappings - schedules Hardware Architecture and Software are It is supported by ■ jointly developed! - system level models - estimation/analysis - analysis & formal verification - simulation Distributed Systems for Real-Time Applications: Analysis and Synthesis 29 Petru Eles May 2003
Platforms and IP-blocks Informal Specification, Requirements Functional Modeling Simulation Formal Arch. Selection System model Verification System Mapping architecture Estimation Scheduling not OK not OK Mapped and scheduled model Simulation Formal OK Verification not OK Softw. model Hardw. model Simulation Softw. Generation Hardw. Synthesis Softw. blocks Hardw. blocks Simulation Prototype Fabrication Distributed Systems for Real-Time Applications: Analysis and Synthesis 30 Petru Eles May 2003
Platforms and IP-blocks Informal Specification, Requirements Functional Modeling Simulation Arch. Selection Formal System model Verification System Mapping architecture Estimation Scheduling Component Mapped and scheduled model library Simulation Formal Verification Softw. model Hardw. model Simulation Softw. Generation Hardw. Synthesis Softw. blocks Hardw. blocks Simulation Prototype Fabrication Distributed Systems for Real-Time Applications: Analysis and Synthesis 31 Petru Eles May 2003
Platforms and IP-blocks Informal Specification, Requirements Functional Modeling Simulation Arch. Selection Formal System model Verification System Mapping architecture Processor Algorithm(s) Architecture Estimation Scheduling Compiler Component Mapped and scheduled model library Simulation Formal Simulator Verification Performance Softw. model Hardw. model Simulation numbers Softw. Generation Hardw. Synthesis Softw. blocks Hardw. blocks Simulation Prototype Fabrication Distributed Systems for Real-Time Applications: Analysis and Synthesis 32 Petru Eles May 2003
Platforms and IP-blocks Informal Specification, Requirements Platform Applications Architecture Functional Modeling Mapping/ Simulation Compiling Arch. Selection Formal System model Verification System Simulator Mapping architecture Estimation Scheduling Performance numbers Component Mapped and scheduled model library Simulation Formal Verification Softw. model Hardw. model Simulation Softw. Generation Hardw. Synthesis Softw. blocks Hardw. blocks Simulation Prototype Fabrication Distributed Systems for Real-Time Applications: Analysis and Synthesis 33 Petru Eles May 2003
Platforms and IP-blocks Informal Specification, Requirements Platform Applications Architecture Functional Modeling Mapping/ Simulation Compiling Arch. Selection Formal System model Verification System Simulator Mapping architecture Estimation Scheduling Performance numbers Component Mapped and scheduled model library Simulation Platform Formal Architecture Verification Platform Softw. model Hardw. model Simulation Application Instance Mapping/ Softw. Generation Hardw. Synthesis Compiling Softw. blocks Hardw. blocks Simulation Simulator Prototype Performance numbers Fabrication Distributed Systems for Real-Time Applications: Analysis and Synthesis 34 Petru Eles May 2003
That’s what’s we are looking at Informal Specification, Requirements Functional Modeling Simulation Formal System model Arch. Selection Verification System Mapping architecture Scheduling Estimation not OK not OK Mapped and scheduled model Simulation Analysis Formal OK Verification Softw. model Hardw. model Simulation Softw. Generation Hardw. Synthesis Softw. blocks Hardw. blocks Simulation Prototype Fabrication Distributed Systems for Real-Time Applications: Analysis and Synthesis 35 Petru Eles May 2003
That’s what’s we are looking at Informal Specification, Requirements Functional Modeling Simulation Formal System model Arch. Selection Verification System Mapping architecture Scheduling Estimation not OK not OK Mapped and scheduled model Simulation Analysis Formal OK Verification Softw. model Hardw. model Simulation Softw. Generation Hardw. Synthesis In the context of Distributed Heterogeneous Systems Softw. blocks Hardw. blocks Simulation Prototype Fabrication Distributed Systems for Real-Time Applications: Analysis and Synthesis 36 Petru Eles May 2003
Outline Embedded Real-Time System ■ System-level Design Flow ■ Distributed Embedded Real-Time Systems ■ Application Model ❚ Heterogeneous Systems ❚ Time/Event Triggered Tasks ❚ Static/Dynamic Communication ❚ Analysis&Optimization ❚ Single/Multi-cluster Heterogeneous Distributed Architectures ■ Analysis&Optimization ❚ Incremental Design Process ■ Distributed Systems for Real-Time Applications: Analysis and Synthesis 37 Petru Eles May 2003
Distributed Embedded Systems Sensors&Actuators ■ ■ ■ I/O Interface RAM CPU ROM ASIC Comm. Controller ■ ■ ■ Distributed Systems for Real-Time Applications: Analysis and Synthesis 38 Petru Eles May 2003
Distributed Embedded Systems ■ ■ ■ NoCs Automotive Electronics ■ ■ ■ ... ... ... ... ... Factory Systems Distributed Systems for Real-Time Applications: Analysis and Synthesis 39 Petru Eles May 2003
Distributed Embedded Systems ■ ■ ■ Why? Physical constraints ■ - Operation close to sensor; Modularity constraints ■ Safety Constraints ■ ■ ■ ■ Performance ■ Distributed Systems for Real-Time Applications: Analysis and Synthesis 40 Petru Eles May 2003
Distributed Embedded Systems Dimensions of Heterogeneity ■ Architectural Components ❚ Hardware/Software ❚ Software Implementation (language, OS) ❚ Data/Control Dominated ❚ Continuous/Discrete ❚ Network Protocol ❚ RT Design Approach/Scheduling Policy ❚ - - - - - - - - - - - - - - - ❚ Distributed Systems for Real-Time Applications: Analysis and Synthesis 41 Petru Eles May 2003
Distributed Embedded Systems ☞ Heterogeneous Nature of Implemented Functions Distributed Systems for Real-Time Applications: Analysis and Synthesis 42 Petru Eles May 2003
Distributed Embedded Systems Engine Control ❚ hard real-time Distributed Systems for Real-Time Applications: Analysis and Synthesis 43 Petru Eles May 2003
Distributed Embedded Systems Engine Control Power Train (break-by-wire, ABS) ❚ hard real-time ❚ hard real-time ❚ highly safety-critical Distributed Systems for Real-Time Applications: Analysis and Synthesis 44 Petru Eles May 2003
Distributed Embedded Systems Engine Control Power Train (break-by-wire, ABS) ❚ hard real-time ❚ hard real-time ❚ highly safety-critical Air Conditioning ❚ soft real-time Distributed Systems for Real-Time Applications: Analysis and Synthesis 45 Petru Eles May 2003
Distributed Embedded Systems Dimensions of Heterogeneity ■ Architectural Components ❚ Hardware/Software ❚ Software Implementation (language, OS) ❚ Data/Control Dominated ❚ Continuous/Discrete ❚ Network Protocol ❚ RT Design Approach/Scheduling Policy ❚ - - - - - - - - - - - - - - - ❚ Distributed Systems for Real-Time Applications: Analysis and Synthesis 46 Petru Eles May 2003
Application Model ☞ An application is modelled as a set of task graphs: Γ 1 Γ 2 Γ 3 Period: T Γ 1 Period: T Γ 3 Period: T Γ 2 Deadline: D Γ 1 Deadline: D Γ 3 Deadline: D Γ 2 Distributed Systems for Real-Time Applications: Analysis and Synthesis 47 Petru Eles May 2003
Application Model ☞ An application is modelled as a set of task graphs: τ 0 τ 1 τ 11 τ 13 τ 3 τ 2 τ 12 τ 6 τ 4 τ 14 τ 15 τ 16 τ 5 τ 8 τ 9 τ 7 τ 10 τ 17 τ 32 Γ 1 Γ 2 Γ 3 Period: T Γ 1 Period: T Γ 3 Period: T Γ 2 Deadline: D Γ 1 Deadline: D Γ 3 Deadline: D Γ 2 Distributed Systems for Real-Time Applications: Analysis and Synthesis 48 Petru Eles May 2003
Application Model ☞ An application is modelled as a set of task graphs: τ 0 C τ 3 τ 1 τ 11 δτ 3 τ 13 τ 2 τ 3 τ 12 τ 6 τ 4 τ 14 τ 15 τ 16 τ 5 τ 8 τ 9 τ 7 τ 10 τ 17 τ 32 Γ 1 Γ 2 Γ 3 Period: T Γ 1 Period: T Γ 3 Period: T Γ 2 Deadline: D Γ 1 Deadline: D Γ 3 Deadline: D Γ 2 Distributed Systems for Real-Time Applications: Analysis and Synthesis 49 Petru Eles May 2003
Application Model ☞ An application is modelled as a set of task graphs: τ 0 Eles et al, IEEE TonVLSI 2000 τ 1 τ 11 D D τ 13 τ 3 τ 2 τ 12 C K C C K τ 6 τ 4 τ 14 τ 15 τ 16 τ 5 τ 8 τ 9 τ 7 τ 10 τ 17 τ 32 Γ 1 Γ 2 Γ 3 Period: T Γ 1 Period: T Γ 3 Period: T Γ 2 Deadline: D Γ 1 Deadline: D Γ 3 Deadline: D Γ 2 Distributed Systems for Real-Time Applications: Analysis and Synthesis 50 Petru Eles May 2003
Application Model ☞ An application is modelled as a set of task graphs: τ 0 D ∧ C ∧ K τ 1 τ 11 D D τ 13 τ 3 τ 2 τ 12 C K C C K τ 6 τ 4 τ 14 τ 15 τ 16 τ 5 τ 8 τ 9 τ 7 τ 10 τ 17 τ 32 Γ 1 Γ 2 Γ 3 Period: T Γ 1 Period: T Γ 3 Period: T Γ 2 Deadline: D Γ 1 Deadline: D Γ 3 Deadline: D Γ 2 Distributed Systems for Real-Time Applications: Analysis and Synthesis 51 Petru Eles May 2003
Application Model ☞ An application is modelled as a set of task graphs: τ 0 D ∧ C ∧ K τ 1 τ 11 D D τ 13 τ 3 τ 2 τ 12 C K C C K τ 6 τ 4 τ 14 τ 15 τ 16 τ 5 τ 8 τ 9 τ 7 τ 10 τ 17 τ 32 Γ 1 Γ 2 Γ 3 Period: T Γ 1 Period: T Γ 3 Period: T Γ 2 Deadline: D Γ 1 Deadline: D Γ 3 Deadline: D Γ 2 Distributed Systems for Real-Time Applications: Analysis and Synthesis 52 Petru Eles May 2003
Heterogeneous Distributed Real-Time Systems RT Design Approach ■ Network Protocol ■ Distributed Systems for Real-Time Applications: Analysis and Synthesis 53 Petru Eles May 2003
Heterogeneous Distributed Real-Time Systems - Time triggered RT Design Approach ■ - Event triggered Network Protocol ■ Distributed Systems for Real-Time Applications: Analysis and Synthesis 54 Petru Eles May 2003
Heterogeneous Distributed Real-Time Systems - Time triggered RT Design Approach ■ - Event triggered - Static Network Protocol ■ - Dynamic Distributed Systems for Real-Time Applications: Analysis and Synthesis 55 Petru Eles May 2003
Time Triggered Systems The execution of tasks is initiated at pre-determined moments in time. ■ Task initiation is performed by the real-time kernel typically based on ■ information stored in a schedule table. Distributed Systems for Real-Time Applications: Analysis and Synthesis 56 Petru Eles May 2003
Time Triggered Systems τ 1 m 1-3 µ Processor µ Processor µ Processor τ 2 τ 3 m 2-4 τ 5 τ 6 τ 4 τ 7 m 7-8 τ 8 Distributed Systems for Real-Time Applications: Analysis and Synthesis 57 Petru Eles May 2003
Time Triggered Systems τ 1 m 1-3 µ Processor µ Processor µ Processor τ 2 τ 3 m 2-4 τ 5 τ 6 0 5 14 τ 4 τ 1 τ 2 µ p1 τ 7 39 6 11 28 44 m 7-8 τ 8 τ 3 τ 6 τ 5 τ 7 µ p2 16 45 τ 8 τ 4 µ p3 bus m 1-3 m 2-4 m 7-8 Distributed Systems for Real-Time Applications: Analysis and Synthesis 58 Petru Eles May 2003
Time Triggered Systems Scheduling Schedule table Task/Comm. Start Time τ 1 0 Static cyclic schedule τ 2 5 τ 3 6 Over a Hyperperiod τ 4 16 τ 5 28 τ 6 11 τ 7 39 τ 8 45 m 1-3 5 m 2-4 14 m 7-8 44 Distributed Systems for Real-Time Applications: Analysis and Synthesis 59 Petru Eles May 2003
Time Triggered Systems Scheduling Schedule table Task/Comm. Start Time τ 1 0 Static cyclic schedule τ 2 5 τ 3 6 Over a Hyperperiod τ 4 16 τ 5 The system is schedulable if it is 28 possible to build a schedule table τ 6 11 such that all deadlines are satisfied. τ 7 39 τ 8 45 m 1-3 5 m 2-4 14 m 7-8 44 Distributed Systems for Real-Time Applications: Analysis and Synthesis 60 Petru Eles May 2003
Time Triggered Systems In the case of Conditional Task Graphs we cannot build a static schedule ■ Quasi-static scheduling Distributed Systems for Real-Time Applications: Analysis and Synthesis 61 Petru Eles May 2003
Time Triggered Systems In the case of Conditional Task Graphs we cannot build a static schedule ■ τ 0 τ 1 τ 11 D D τ 13 τ 3 τ 12 τ 2 C K C C K τ 6 τ 4 τ 14 τ 15 τ 16 τ 5 τ 8 τ 9 µ Processor µ Processor τ 7 τ 10 τ 17 τ 32 µ Processor Distributed Systems for Real-Time Applications: Analysis and Synthesis 62 Petru Eles May 2003
Time Triggered Systems Eles et al, IEEE TonVLSI 2000 D D ∧ C D ∧ C ∧ K D ∧ C ∧ K D ∧ C D ∧ C ∧ K D ∧ C ∧ K D ∧ C D ∧ C true D τ 1 0 τ 2 3 τ 10 34 34 26 26 34 26 τ 11 0 τ 14 35 24 τ 17 29 37 30 26 22 24 τ 18 (1 → 3) 3 τ 19 (2 → 5) 9 10 τ 20 (3 → 10) 28 20 21 21 22 18 D 6 C 7 7 K 15 15 Distributed Systems for Real-Time Applications: Analysis and Synthesis 63 Petru Eles May 2003
Time Triggered Systems Why do we like (quasi)static cyclic scheduling? High predictability ■ Easy to debug/validate ■ Low execution time overhead ■ Suitable for safety-critical applications Distributed Systems for Real-Time Applications: Analysis and Synthesis 64 Petru Eles May 2003
Time Triggered Systems Some problems with (quasi)static cyclic scheduling: Not flexible: ■ quality degrades rapidly if periods and execution times deviate from ❚ those predicted; if new tasks are added, the whole schedule has to be regenerated. ❚ Static scheduling for large task sets is computationally very expensive. ■ Urgent events (interrupts) are handled purely: ■ time slots are statically allocated for polling and handling such events. ❚ Very long hyper-periods have to be avoided: ■ the periods of individual tasks have to be adjusted; ❚ this can lead to artificially reduced periods ⇒ artificially increased load ⇒ waste of processor time. Tasks have to be “manually” split, in order to make the system schedulable. ■ Distributed Systems for Real-Time Applications: Analysis and Synthesis 65 Petru Eles May 2003
Event Triggered Systems The execution of tasks is initiated by the occurrence of a certain event. ■ Task initiation is performed by the real-time kernel which selects and ■ executes the ready task with the highest priority. Task scheduling is, typically, preemptive. ■ No schedule (predetermined activation times) is generated off-line. ■ Distributed Systems for Real-Time Applications: Analysis and Synthesis 66 Petru Eles May 2003
Event Triggered Systems τ 1 a 2 m 1 m 2 a 3 0 τ 2 τ 3 O 1,2 = O 1,3 O 1 τ 1 µ p1 priority m1 < priority m2 O 2 priority τ 2 > priority τ 3 µ p2 O 3 µ Processor µ Processor ❚ Arrival time a i : The time at which τ i becomes ready for execution. ❚ Offset O i : The earliest possible arrival time of τ i . Distributed Systems for Real-Time Applications: Analysis and Synthesis 67 Petru Eles May 2003
Event Triggered Systems τ 1 a 2 m 1 m 2 a 3 0 τ 2 τ 3 O 1 τ 1 µ p1 priority m1 < priority m2 O 2 priority τ 2 > priority τ 3 µ p2 O 3 µ Processor µ Processor m 2 bus Distributed Systems for Real-Time Applications: Analysis and Synthesis 68 Petru Eles May 2003
Event Triggered Systems τ 1 a 2 m 1 m 2 a 3 0 τ 2 τ 3 O 1 τ 1 µ p1 J 2 priority m1 < priority m2 O 2 priority τ 2 > priority τ 3 µ p2 s 3 J 3 O 3 τ 3 µ Processor µ Processor m 2 m 1 bus ❚ Start time s i : Time when a task starts execution. ❚ Release jitter J i : The delay between the arrival of τ i and the start of its execution. Distributed Systems for Real-Time Applications: Analysis and Synthesis 69 Petru Eles May 2003
Event Triggered Systems τ 1 a 2 m 1 m 2 a 3 0 τ 2 τ 3 O 1 τ 1 µ p1 J 2 priority m1 < priority m2 O 2 τ 2 priority τ 2 > priority τ 3 µ p2 s 3 J 3 w 3 O 3 τ 3 µ Processor w m1 µ Processor m 2 m 1 bus ❚ Interference w i : The time τ i is preempted by higher priority tasks. ❚ Queuing delay w mi : The delay experienced by m i before being sent. Distributed Systems for Real-Time Applications: Analysis and Synthesis 70 Petru Eles May 2003
Event Triggered Systems τ 1 a 2 m 1 m 2 a 3 0 r 3 τ 2 τ 3 O 1 τ 1 µ p1 r 2 J 2 priority m1 < priority m2 O 2 τ 2 priority τ 2 > priority τ 3 µ p2 s 3 J 3 w 3 O 3 τ 3 τ 3 µ Processor w m1 µ Processor m 2 m 1 bus ❚ Response time r i : The time from the arrival of τ i until it finishes execution. Distributed Systems for Real-Time Applications: Analysis and Synthesis 71 Petru Eles May 2003
Event Triggered Systems Schedulability analysis (is the system schedulable?) Distributed Systems for Real-Time Applications: Analysis and Synthesis 72 Petru Eles May 2003
Event Triggered Systems Schedulability analysis (is the system schedulable?) Utilisation based tests ■ Feasibility test for processes with RM priority assignment ❚ (Liu&Layland ‘73): 1 n - - - C i ∑ n ≤ - - - - - n 2 – 1 T i i = 1 Problems: ❚ - Such tests are valid only under restrictive conditions. - They are pessimistic. - Necessary and sufficient tests (if available) are computationally expensive. Distributed Systems for Real-Time Applications: Analysis and Synthesis 73 Petru Eles May 2003
Event Triggered Systems Schedulability analysis (is the system schedulable?) Response time analysis ■ Calculate worst case response time r i for each task τ i . ❚ If, for each task r i ≤ D i , then and only then the task set is schedulable. The basic equation (Audslay et al ‘91): ❚ This is the interference w i ∑ r i from higher r i = C i + - C j - - - - T j priority tasks. ∀ ∈ hp τ i ( ) j Problem ❚ - The above formula is exact (necessary and sufficient) only in particular cases (monoprocessor, independent tasks, etc.). - In more general cases (e.g. data dependencies) it is very pessimistic. Distributed Systems for Real-Time Applications: Analysis and Synthesis 74 Petru Eles May 2003
Event Triggered Systems Response time calculation for data dependent tasks (Tindell ‘94): , where the interference is r i = J i + w i + C i ∑ w i + J j – O ij w i = C - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - j T j ∀ ∈ hp τ i ( ) 0 j Distributed Systems for Real-Time Applications: Analysis and Synthesis 75 Petru Eles May 2003
Event Triggered Systems Response time calculation for data dependent tasks (Tindell ‘94): , where the interference w i is: r i = J i + w i + C i ∑ w i + J j – O ij w i = C - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - j T j ∀ ∈ hp τ i ( ) 0 j Main idea: ■ - Use offsets and jitter to model dependencies The same idea can be used to model communication in distributed systems ■ (the release jitter of the receiver task depends on the communication delay). Further reduce pessimism in the case with conditional execution ■ (Pop, Eles, Peng, CODES 2000). Distributed Systems for Real-Time Applications: Analysis and Synthesis 76 Petru Eles May 2003
Static Communication: TTP Network Sensors&Actuators N 0 N n N 1 ■ ■ ■ I/O Interface RAM CPU ROM ASIC TTP Controller TTP cycle TTP round 1 TTP round 2 S 0 S 1 S n S 0 S 1 S n left empty in N 0 writes N 1 writes this round Distributed Systems for Real-Time Applications: Analysis and Synthesis 77 Petru Eles May 2003
Static Communication: TTP Network Sensors&Actuators N 0 N n N 1 ■ ■ ■ I/O Interface RAM CPU ROM ASIC TTP Controller length Time Action (bits) Over a TTP cycle t 1 rd-frame 16 t 2 wr-frame 32 t 3 rd-frame 32 ... ... ... t x wr-frame 16 Distributed Systems for Real-Time Applications: Analysis and Synthesis 78 Petru Eles May 2003
Dynamic Communication: CAN Network Sensors&Actuators N 0 N n N 1 ■ ■ ■ I/O Interface RAM CPU ROM ASIC CAN frame Comm. Controller Identifier Data field CRC, etc. Priority bus with collision avoidance mechanism: ■ The node that transmits the highest priority frame wins the contention. Distributed Systems for Real-Time Applications: Analysis and Synthesis 79 Petru Eles May 2003
Scheduling of Distributed RT Systems The classical approaches: ■ TT tasks over static network. ❚ (Eles et al, IEEE TonVLSI 2000) ET tasks over dynamic network. ❚ (Tindell et al ‘95) Distributed Systems for Real-Time Applications: Analysis and Synthesis 80 Petru Eles May 2003
Scheduling of Distributed RT Systems The classical approaches: ■ TT tasks over static network. ❚ (Eles et al, IEEE TonVLSI 2000) ET tasks over dynamic network. ❚ (Tindell et al ‘95) A first step towards heterogeneous systems: ■ TT tasks over dynamic network. ❚ (Dobrin et al, 2001) ET tasks over static networks. ❚ (Tindell ‘94; Pop, Eles, Peng, DATE 2000 & RT Systems Journal 2003) Distributed Systems for Real-Time Applications: Analysis and Synthesis 81 Petru Eles May 2003
Optimization of Distributed RT Systems ☞ Once a scheduling/schedulability analysis approach is in place, several optimization tasks can be performed. Distributed Systems for Real-Time Applications: Analysis and Synthesis 82 Petru Eles May 2003
Optimization of Distributed RT Systems ☞ Once a scheduling/schedulability analysis approach is in place, several optimization tasks can be performed. System model Arch. Selection System Mapping architecture Scheduling Estimation not OK not OK Mapped and scheduled model OK Analysis Distributed Systems for Real-Time Applications: Analysis and Synthesis 83 Petru Eles May 2003
Optimization of Distributed RT Systems ☞ Once a scheduling/schedulability analysis approach is in place, several optimization tasks can be performed. Task mapping ■ Bus access optimization ■ Pop, Eles, Peng, CODES ‘99 Pop, Eles, T. Pop, Peng, DAC ‘01 Pop, Eles, Peng, RT Systems Journal 2003 Distributed Systems for Real-Time Applications: Analysis and Synthesis 84 Petru Eles May 2003
Task Mapping N 1 N 3 N 2 τ 1 TTP round slow fast S 1 S 2 S 3 τ 2 τ 4 S1 = S2 = S3 = 4ms τ 3 T = D = 50ms N 1 N 2 N 3 τ 1 4ms - - τ 2 12ms 8ms - τ 3 4ms - - τ 4 12ms 8ms - Distributed Systems for Real-Time Applications: Analysis and Synthesis 85 Petru Eles May 2003
Task Mapping N 1 N 3 N 2 τ 1 TTP round m 1,2 m 1,4 slow fast S 1 S 2 S 3 τ 2 τ 4 S1 = S2 = S3 = 4ms m 2,3 m 4,3 τ 3 0ms 4ms 52ms T = D = 50ms τ 1 τ 3 N 1 N 1 N 2 N 3 τ 2 τ 4 N 3 τ 1 4ms - - τ 2 12ms 8ms - τ 3 m 1,2 m 1,4 m 2,3 m 4,3 Bus 4ms - - τ 4 S 1 S 2 S 3 S 1 S 2 S 3 S 1 S 2 S 3 S 1 S 2 S 3 S 1 12ms 8ms - Distributed Systems for Real-Time Applications: Analysis and Synthesis 86 Petru Eles May 2003
Task Mapping N 1 N 3 N 2 τ 1 TTP round m 1,2 m 1,4 slow fast S 1 S 2 S 3 τ 2 τ 4 S1 = S2 = S3 = 4ms m 2,3 m 4,3 τ 3 0ms 4ms 48ms T = D = 50ms τ 1 τ 3 N 1 N 1 N 2 N 3 τ 2 τ 4 N 2 τ 1 4ms - - τ 2 12ms 8ms - τ 3 m 1,2 m 1,4 m 2,3 m 4,3 Bus 4ms - - τ 4 S 1 S 2 S 3 S 1 S 2 S 3 S 1 S 2 S 3 S 1 S 2 S 3 S 1 12ms 8ms - Distributed Systems for Real-Time Applications: Analysis and Synthesis 87 Petru Eles May 2003
Bus Access Optimization N 1 N 2 τ 1 TTP round m 1,2 m 1,4 S 1 S 2 τ 2 τ 4 m 2,3 m 4,3 τ 3 Distributed Systems for Real-Time Applications: Analysis and Synthesis 88 Petru Eles May 2003
Bus Access Optimization N 1 N 2 τ 1 TTP round m 1,2 m 1,4 S 1 S 2 τ 2 τ 4 m 2,3 m 4,3 τ 3 26ms τ 1 τ 3 N 1 τ 2 τ 4 N 2 m 1,2 m 1,4 m 2,3 m 4,3 Bus S 1 S 2 S 1 S 2 S 1 S 2 Distributed Systems for Real-Time Applications: Analysis and Synthesis 89 Petru Eles May 2003
Bus Access Optimization N 1 N 2 τ 1 TTP round m 1,2 m 1,4 S 2 S 1 τ 2 τ 4 m 2,3 m 4,3 τ 3 24ms τ 1 τ 3 τ 3 N 1 τ 2 τ 4 N 2 m 1,4 m 2,3 m 4,3 m 1,2 Bus S 2 S 1 S 2 S 1 S 2 S 1 S 2 S 1 S 2 S 1 Distributed Systems for Real-Time Applications: Analysis and Synthesis 90 Petru Eles May 2003
Bus Access Optimization N 1 N 2 τ 1 TTP round m 1,2 m 1,4 S 1 S 2 τ 2 τ 4 m 2,3 m 4,3 τ 3 22ms τ 1 τ 3 τ 3 N 1 τ 2 τ 4 N 2 m 1,2 m 1,4 m 2,3 m 4,3 Bus S 1 S 2 S 1 S 2 S 1 S 2 S 1 S 2 S 1 S 2 Distributed Systems for Real-Time Applications: Analysis and Synthesis 91 Petru Eles May 2003
Outline Embedded Real-Time System ■ System-level Design Flow ■ Distributed Embedded Real-Time Systems ■ Application Model ❚ Heterogeneous Systems ❚ Time/Event Triggered Tasks ❚ Static/Dynamic Communication ❚ Analysis&Optimization ❚ Single/Multi-cluster Heterogeneous Distributed Architectures ■ Analysis&Optimization ❚ Incremental Design Process ■ Distributed Systems for Real-Time Applications: Analysis and Synthesis 92 Petru Eles May 2003
The Traditional Approach One node One function ■ ■ ■ ■ ■ ■ Distributed Systems for Real-Time Applications: Analysis and Synthesis 93 Petru Eles May 2003
The Traditional Approach One node One function ■ ■ ■ Purchase node&function and ■ integrate into system Sophistication grew quickly ■ More then 100 nodes ■ ■ ■ Resources have to be used more efficiently Distributed Systems for Real-Time Applications: Analysis and Synthesis 94 Petru Eles May 2003
What Comes One node Several functions Several nodes One function ■ ■ ■ Flexibility! Reduce cost ■ Improve resource usage ■ Function close to sensor ■ ■ ■ ■ Distributed Systems for Real-Time Applications: Analysis and Synthesis 95 Petru Eles May 2003
What Comes One node Several functions Several nodes One function ■ ■ ■ Flexibility! Reduce cost ■ Improve resource usage ■ Function close to sensor ■ ☞ Needed: ■ ■ ■ Middleware software ■ New analysis ■ New system optimization ■ Distributed Systems for Real-Time Applications: Analysis and Synthesis 96 Petru Eles May 2003
Multi-cluster Heterogeneous Distributed Architecture Time triggered cluster: TT tasks ❚ ■ ■ ■ Static communication ❚ That we have seen. Event triggered cluster: ET tasks ❚ ■ ■ ■ Dynamic communication ❚ Distributed Systems for Real-Time Applications: Analysis and Synthesis 97 Petru Eles May 2003
Multi-cluster Heterogeneous Distributed Architecture ■ ■ ■ Analyse this! ■ ■ ■ Distributed Systems for Real-Time Applications: Analysis and Synthesis 98 Petru Eles May 2003
Single-cluster Heterogeneous Distributed Architecture N 0 N n N 1 ET tasks ■ ■ ■ TT tasks Bus cycle static dynamic static dynamic static phase phase phase phase phase Distributed Systems for Real-Time Applications: Analysis and Synthesis 99 Petru Eles May 2003
Single-cluster Heterogeneous Distributed Architecture N 0 N n N 1 ET tasks ■ ■ ■ TT tasks Bus cycle S 0 S 1 S 2 S 3 S 4 S 5 S n Distributed Systems for Real-Time Applications: Analysis and Synthesis 100 Petru Eles May 2003
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