Distributed Synthesis for Well Connected Architectures Paul Gastin, - PowerPoint PPT Presentation

Distributed Synthesis for Well Connected Architectures Paul Gastin, Nathalie Sznajder and Marc Zeitoun March 13th 2006 ACI Cortos Persee Versydis

Synthesis of a reactive system inputs from E outputs to E Specification Open system S ϕ

Synthesis of a reactive system inputs from E outputs to E Specification Open system S ϕ Program P Two problems Decide whether there exists a program st. P || E | = ϕ , ∀ E . Synthesis: If so, compute such a program. For reasonable systems and specifications, the problems are decidable.

Distributed synthesis input of E output to E Open distributed system S S 1 S 2 Specification ϕ S 3 S 4

Distributed synthesis input of E output to E Open distributed system S S 1 P 1 P 2 S 2 Specification ϕ S 3 P 3 P 4 S 4 Two problems Decide the existence of a distributed program such that their joint behavior P 1 || P 2 || P 3 || P 4 || E satisfies ϕ , for all E . Synthesis : If it exists, compute such a distributed program.

Distributed synthesis input of E output to E Open distributed system S P 1 S 1 P 2 S 2 Specification ϕ S 3 P 3 P 4 S 4 Two problems Decide the existence of a distributed program such that their joint behavior P 1 || P 2 || P 3 || P 4 || E satisfies ϕ , for all E . Synthesis : If it exists, compute such a distributed program. Peterson-Reif 1979, Pnueli-Rosner 1990 In general, the problem is undecidable.

The model Example a 1 x 1 a 4 x 4 x 0 x 3 a 2 x 2 a 3 x 5

The model Example a 1 x 1 a 4 x 4 x 0 x 3 a 2 x 2 a 3 x 5 Synchronous behavior

The model Example a 1 x 1 a 4 x 4 x 0 x 3 a 2 x 2 a 3 x 5 Synchronous behavior Strategies with local memory

The model Example a 1 x 1 a 4 x 4 x 0 x 3 a 2 x 2 a 3 x 5 Synchronous behavior Strategies with local memory 0-delay semantics

The model Example a 1 x 1 a 4 x 4 x 0 x 3 a 2 x 2 a 3 x 5 Synchronous behavior Strategies with local memory 0-delay semantics Input-output specifications

Undecidable architecture (Pnueli–Rosner ’90) x 0 y 0 P 0 x 1 y 1 P 1

Undecidable architecture (Pnueli–Rosner ’90) S x 0 y 0 P 0 x 1 y 1 P 1

Undecidable architecture (Pnueli–Rosner ’90) S x 0 y 0 P 0 $ C i $ T x 1 y 1 P 1 $ C ′ i $

Undecidable architecture (Pnueli–Rosner ’90) S x 0 y 0 P 0 $ C i +1 $ $ C i $ ⇒ T T x 1 y 1 $ C ′ i +1 $ P 1 $ C ′ i $

Decidable architecture x 0 y 0 P 0 t y 1 x 1 P 1

Pipe-line decidable for global specifications (Kupferman–Vardi ’01) . . . O env P 1 O 1 P 2 O 2 O n − 1 P n O n

Pipe-line decidable for global specifications (Kupferman–Vardi ’01) . . . O env P 1 O 1 P 2 O 2 O n − 1 P n O n

Pipe-line decidable for global specifications (Kupferman–Vardi ’01) . . . O env P 1 O 1 P 2 O 2 O n − 1 P n O n

Information fork criterion (Finkbeiner–Schewe ’05) x 0 x 1 p 0 p 1 t 0 t 1 p y

Information fork criterion (Finkbeiner–Schewe ’05) x 0 x 1 x 0 x 1 p 0 p 1 p 0 p 1 t 0 t 1 t 0 t 1 p y

Outline Uncomparable information 1 Uniformly well connected architectures 2 Well connected architectures 3

Outline Uncomparable information 1 Uniformly well connected architectures 2 Well connected architectures 3

Uncomparable information yields undecidability Definition For an output variable v , View( v ) is the set of input variables u such that v is accessible from u . Definition An architecture has uncomparable information if there exist x , y output variables such that View( x ) \ View( y ) � = ∅ and View( y ) \ View( x ) � = ∅ . Otherwise it is said to have preordered information. x 0 x 1 y 0 y 1

Uncomparable information yields undecidability Theorem Architectures with uncomparable information are undecidable for LTL or CTL input-output specifications. Proof LTL specifications : x 0 x 1 x 0 x 1 y 0 y 1 y 0 y 1

Uncomparable information yields undecidability Theorem Architectures with uncomparable information are undecidable for LTL or CTL input-output specifications. Proof LTL specifications : x 0 x 1 x 0 x 1 y 0 y 1 y 0 y 1

Uncomparable information yields undecidability Theorem Architectures with uncomparable information are undecidable for LTL or CTL input-output specifications. Proof LTL specifications : x 0 x 1 x 0 x 1 0 0 0 0 0 0 0 0 y 0 y 1 y 0 y 1

Outline Uncomparable information 1 Uniformly well connected architectures 2 Well connected architectures 3

Uniformly well connected architectures Definition An architecture is uniformly well connected if there is a uniform way to route variables in View( v ) to v for each output variable v . u v w p  p  s t p  p  p  y x z

Uniformly well connected architectures Definition An architecture is uniformly well connected if there is a uniform way to route variables in View( v ) to v for each output variable v . u v w p  p  s t u ⊕ v v ⊕ w p  p  p  y x z

Network Information Flow M  M  M  M  s  s  s  a c b d e g f demands demands M  , M  , M  , M  M  , M 

Network Information Flow : Multicast M  M  M  M  s a c b d e g f demands demands M  , M  , M  , M  M  , M  , M  , M 

Relations between the two problems Theorem The multicast reduces to checking uniform well connectedness.

Relations between the two problems Theorem The multicast reduces to checking uniform well connectedness. Proof. M  M  s a c b e f d

Relations between the two problems Theorem The multicast reduces to checking uniform well connectedness. Proof. M  M  M  M  s s u v w a c a c b b y z s t x r e f e f d d y  y  y 

Relations between the two problems Theorem Checking uniform well connectedness reduces to the network information flow.

Relations between the two problems Theorem Checking uniform well connectedness reduces to the network information flow. Proof. s

Relations between the two problems Theorem Checking uniform well connectedness reduces to the network information flow. Proof. s s demands s demands s

Relations between the two problems Theorem Checking uniform well connectedness reduces to the network information flow. Proof. s s demands s demands s

Relations between the two problems Theorem Checking uniform well connectedness reduces to the network information flow. Proof. s s demands s demands s

Complexity Rasala Lehman-Lehman 2004 Multicast whith alphabet size q = p k (where p is prime) is NP-hard.

Complexity Rasala Lehman-Lehman 2004 Multicast whith alphabet size q = p k (where p is prime) is NP-hard. Theorem Checking whether a given architecture is uniformly well connected is NP-complete.

Complexity Rasala Lehman-Lehman 2004 Multicast whith alphabet size q = p k (where p is prime) is NP-hard. Theorem Checking whether a given architecture is uniformly well connected is NP-complete. Proof. It is trivially NP. Reduction from multicast gives NP-hardness.

Decidability criterion for uniformly well connected architectures Theorem Architectures with preordered information are decidable for CTL* specifications.

Decidability criterion for uniformly well connected architectures Theorem Architectures with preordered information are decidable for CTL* specifications. Proof. x 1 x 2 x 3 x 4 y 1 y 2 y 3 y 4

Decidability criterion for uniformly well connected architectures Theorem Architectures with preordered information are decidable for CTL* specifications. Proof. x 1 x 2 x 3 x 4 y 1 y 2 y 3 y 4

Decidability criterion for uniformly well connected architectures Theorem Architectures with preordered information are decidable for CTL* specifications. Proof. x 1 x 2 x 3 x 4 y 1 y 2 y 3 y 4

Decidability criterion for uniformly well connected architectures Theorem Architectures with preordered information are decidable for CTL* specifications. Proof. x 1 x 2 x 3 x 4 y 1 y 2 y 3 y 4

Decidability criterion for uniformly well connected architectures Theorem Architectures with preordered information are decidable for CTL* specifications. Proof. x 1 x 1 x 2 x 3 x 4 x 2 x 2 x 3 x 3 x 3 x 4 x 4 x 4 x 4 a 1 a 2 a 3 a 4 y 1 y 2 y 3 y 4 y 1 y 2 y 3 y 4 Theorem: Kupferman-Vardi (LICS’01) The synthesis problem with local strategies is decidable for pipeline archi- tectures and CTL ∗ specifications (or tree-automata specifications) on all variables.

Outline Uncomparable information 1 Uniformly well connected architectures 2 Well connected architectures 3

Well connected architectures Definition An architecture is well connected if, for each output variable y , the subarchitecture formed by E ∗− 1 ( y ) is uniformly well connected. u v w p  p  s t p  p  p  y x z

Well connected architectures Definition An architecture is well connected if, for each output variable y , the subarchitecture formed by E ∗− 1 ( y ) is uniformly well connected. u v w p  p  s t v p  p  p  y x z

Well connected architectures Definition An architecture is well connected if, for each output variable y , the subarchitecture formed by E ∗− 1 ( y ) is uniformly well connected. u v w p  p  s t u w p  p  p  y x z