Digital System Design Lecture 12: Altera-Xilinx SOPC Amir Masoud Gharehbaghi amgh@mehr.sharif.edu
Altera Nios-II � CPU Architecture � 32-bit general-purpose processor (instruction, data, address) � 32 general-purpose registers � 32 external interrupt sources � On-Chip Debugging � JTAG-Based � Custom Instructions � Up to 256 user-defined instructions Sharif University of Technology 2
Nios-II Family � Three versions � Fast (Nios-II/ f): Optimized for maximum performance � Economy (Nios-II/ e): Optimized for minimum logic usage � Standard (Nios-II/ s): Offers a balance between performance and size Sharif University of Technology 3
Nios-II Family Summary Feature Nios-II/ e Nios-II/ s Nios-II/ f Size (LEs) < 600 < 1300 < 1800 Frequency (max) 150 MHz 135 MHz 135 MHz Pipeline stages - 5 6 Instruction Cache - 512 B - 512 B - 64 KB 64 KB Data Cache - - 512 B - 64 KB Branch prediction - Static Dynamic Custom Instructions 256 256 256 Sharif University of Technology 4
Nios-II Device Support � Stratix-II: � Highest-performance, highest-density � Stratix: � High-performance, high-density � Stratix GX: � High-performance architecture with high-speed serial transceivers � Cyclone-II: � Lowest-cost FPGA � Cyclone: � Low-cost ASIC replacement � HardCopy-II & HardCopy: � The industry’s first structured ASIC that offers a comprehensive alternative to traditional ASICs Sharif University of Technology 5
Additional IP Megafunctions � PCI Controller 32 & 64 bits � UART � Floating Point Arithmetic Unit � DMA Controller � Ethernet MAC (1000/ 100/ 10 Mbps) � USB Controller � Serial ATA Controller � … Sharif University of Technology 6
Development Tools � Hardware Generation: � SOPC Builder � Quartus-II � Software Development: � Nios-II IDE Sharif University of Technology 7
Cyclone-II Block Diagram Sharif University of Technology 8
Cyclone-II Feature Summary Sharif University of Technology 9
Stratix-II Block Diagram Sharif University of Technology 10
Stratix-II Feature Summary Sharif University of Technology 11
Sharif University of Technology 12
Xilinx Virtex-4 Family � Three Families: � Virtex-4 LX: � High-performance logic applications solution � Virtex-4 FX: � High-performance, full-featured solution for embedded platform applications � Virtex-4 SX: � High-performance solution for Digital Signal Processing (DSP) applications Sharif University of Technology 13
Virtex-4 Family Overview Sharif University of Technology 14
Virtex-4 FX Feature Overview Sharif University of Technology 15
RocketIO Multi Gigabit Tranceiver � Full-duplex serial transceiver (MGT) capable of 622 Mb/ s to 10+ Gb/ s baud rates � CRC generation and checking � Receiver signal detect and loss of signal indicator � … Sharif University of Technology 16
PowerPC 405 RISC Core � 32-bit RISC Processor � Up to 450 MHz operation � Five-stage data path pipeline � 16 KB instruction cache � 16 KB data cache � Auxiliary Processor Unit (APU) Interface � … Sharif University of Technology 17
Tri-mode Ethernet Media Access Controller (MAC) � IEEE 802.3 compliant � Operates at 10, 100, and 1,000 Mb/ s � Supports tri-mode auto-detect � Half or Full Duplex � Flexible, user-configurable host interface � … Sharif University of Technology 18
Xilinx Design Tools � Logic Design � ISE � Embedded Design � EDK � ChipScope Pro � System Generator (DSP) Sharif University of Technology 19
IP Cores � Audio, Video, Image, DSP � JPEG, JPEG2000, MPEG, SPDIF, … � Bus Interface, Comunication & Networking � PCI, PCI-X, USB, Bluetooth, USB, … � Math � CORDIC, Floating point, FFT, … � … Sharif University of Technology 20
Recommend
More recommend
