Digital Logic Design: a rigorous approach c � Chapters 17-20: Flip-Flops, Synchronous Circuits, and Finite State Machines Guy Even Moti Medina School of Electrical Engineering Tel-Aviv Univ. May 31, 2020 Book Homepage: http://www.eng.tau.ac.il/~guy/Even-Medina 1 / 75
Preliminary questions How is time measured in a synchronous circuit? 1 What is a “clock” in a microprocessor? 2 What is the frequency of a clock? 3 What is memory? How are bits stored? 4 2 / 75
The clock the clock is generated by rectifying and amplifying a signal generated by special non-digital devices (e.g., crystal oscillators). Definition A clock is a periodic logical signal that oscillates instantaneously between logical one and logical zero. There are two instantaneous transitions in every clock period: (i) in the beginning of the clock period, the clock transitions instantaneously from zero to one; and (ii) at some time in the interior of the clock period, the clock transitions instantaneously from one to zero. logical level clock fall clock rise clock period 1 pulse width 0 time 3 / 75
Clock cycles A clock partitions time into discrete intervals. t i - the starting time of the i th clock cycle. [ t i , t i +1 ) -clock cycle i . Clock period = t i +1 − t i . Assumption We assume that the clock period equals 1. t i +1 = t i + 1 . 4 / 75
Flip-Flop Definition A flip-flop is defined as follows. Inputs: Digital signals D ( t ) and a clock clk . Output: A digital signal Q ( t ). Functionality: Q ( t + 1) = D ( t ) . t D [ t ] Q [ t ] 0 1 ? 1 0 1 2 0 0 3 1 0 4 1 1 5 / 75
Clock enabled flip-flops Definition A clock enabled flip-flop is defined as follows. Inputs: Digital signals D ( t ) , ce ( t ) and a clock clk . Output: A digital signal Q ( t ). Functionality: � D ( t ) if ce ( t ) = 1 Q ( t + 1) = Q ( t ) if ce ( t ) = 0. We refer to the input signal ce ( t ) as the clock-enable signal. Note that the input ce ( t ) indicates whether the flip-flop samples the input D ( t ) or maintains its previous value. 6 / 75
Which design is a correct clock enabled FF? D ( t ) D ( t ) 1 0 ce ( t ) mux ce ( t ) and clk ff ff clk Q ( t ) Q ( t ) (A) (B) 7 / 75
The Zero Delay Model Transitions of all signals are instantaneous. 1 Combinational gates: t pd = t cont = 0. 2 Flip-flops satisfy: 3 Q ( t + 1) = D ( t ) . Simplified model for specifying and simulating the 4 functionality of circuits with flip-flops. For a signal X , let X i denote its value during the i th clock 5 cycle. 8 / 75
Example: Sequential xor A xor Y D ff i A i Y i Z i clk 0 0 0 0 Q 1 0 0 0 2 1 1 0 3 0 1 1 Z 4 0 1 1 5 1 0 1 6 0 0 0 7 1 1 0 8 0 1 1 9 / 75
Sequential Adder Definition A sequential adder is defined as follows. Inputs: A , B and a clock signal clk , where A i , B i ∈ { 0 , 1 } . Output: S , where S i ∈ { 0 , 1 } . Functionality: Then, for every i ≥ 0, � A [ i : 0] � + � B [ i : 0] � = � S [ i : 0] � (mod 2 i +1 ). 10 / 75
Sequential Adder Implementation 11 / 75
Sequential Adder: Correctness Theorem i i i A j · 2 j + B j · 2 j = S j · 2 j + c out ( i ) · 2 i +1 . � � � j =0 j =0 j =0 Proof. The proof is by induction on i . The induction basis for i = 0 follows from the functionality of the full-adder: A 0 + B 0 + C in (0) = 2 · C out (0) + S 0 . This requires that C in (0) = 0! Namely, that the FF is initialized to zero. (We will discuss how to partly mitigate the issue of initialization later.) 12 / 75
Sequential Adder: Implementation - correctness (cont.) Proof. We now prove the induction step for i > 0. i − 1 i − 1 i i A j · 2 j + B j · 2 j = ( A i + B i ) · 2 i + A j · 2 j + � � � � B j · 2 j j =0 j =0 j =0 j =0 i − 1 = ( A i + B i ) · 2 i + S j · 2 j + C out ( i − 1) · 2 i � j =0 i − 1 = ( C in ( i ) + A i + B i ) · 2 i + � S j · 2 j j =0 i − 1 = ( S i + 2 · C out ( i )) · 2 i + � S j · 2 j j =0 i S j · 2 j + C out ( i ) · 2 i +1 . � = j =0 13 / 75
Relation between rca ( n ) and Sequential Adder fa i is “simulated” by the fa (in Seq. Adder) in the i ’th clock 1 cycle. We can view rca ( n ) as an “unrolling” of the Seq. Adder. 2 B [ n − 1] A [ n − 1] B [ n − 2] A [ n − 2] B [1] A [1] B [0] A [0] C [0] fa n − 1 fa n − 2 c fa 1 c fa 0 c s c s s s C [ n ] S [ n − 1] C [ n − 1] S [ n − 2] C [ n − 2] C [2] S [1] C [1] S [0] 14 / 75
Comparison with Combinational Lower Bounds Addition and xor n have functional cone of size n . 1 Every combinational circuit has cost Ω( n ) and delay Ω(log n ). 2 But sequential versions have cost O (1)! How can that be? 3 15 / 75
Registers A term register is used to define a memory device that stores a bit or more. There are two main types of register depending on how their contents are loaded. Parallel Load Register 1 Shift Register (also called a serial load register) 2 16 / 75
Parallel Load Register - specification Definition An n -bit parallel load register is specified as follows. Inputs: D [ n − 1 : 0]( t ), ce ( t ), and a clock clk . Output: Q [ n − 1 : 0]( t ). Functionality: � D [ n − 1 : 0]( t ) if ce ( t ) = 1 Q [ n − 1 : 0]( t + 1) = Q [ n − 1 : 0]( t ) if ce ( t ) = 0. An n -bit parallel load register is simply built from n clock enabled flip-flops. 17 / 75
Parallel Load Register - design D [3 : 0] 4 clk ce-ff (4) ce 4 Q [3 : 0] D [3] D [2] D [1] D [0] 1 1 1 1 clk clk clk clk ce-ff ce-ff ce-ff ce-ff ce ce ce ce 1 1 1 1 Q [3] Q [2] Q [1] Q [0] Figure: A 4-bit parallel load register 18 / 75
Parallel Load Register - simulation D [3] D [2] D [1] D [0] 1 1 1 1 clk clk clk clk ce-ff ce-ff ce-ff ce-ff ce ce ce ce 1 1 1 1 Q [3] Q [2] Q [1] Q [0] D [3 : 0] Q [3 : 0] i ce 0 1010 1 0000 1 0101 1 1010 2 1100 0 0101 3 1100 1 0101 4 0011 1 1100 19 / 75
Shift Register - definition Definition A shift register of n bits is defined as follows. Inputs: D [0]( t ) and a clock clk . Output: Q [ n − 1]( t ). Functionality: Q [ n − 1]( t + n ) = D [0]( t ). 20 / 75
Shift Register - design D [3] D [2] D [1] D [0] 1 1 1 1 clk clk clk clk ff 3 ff 2 ff 1 ff 0 1 1 1 1 Q [3] Q [2] Q [1] Q [0] Figure: A 4-bit shift register. Functionality: Q [3]( t + 4) = D [0]( t ) 21 / 75
Shift Registers - simulation D [3] D [2] D [1] D [0] 1 1 1 1 clk clk clk clk ff 3 ff 2 ff 1 ff 0 1 1 1 1 Q [3] Q [2] Q [1] Q [0] i D [0] Q [3 : 0] 0 1 0000 1 1 0001 2 1 0011 3 0 0111 4 1 1110 22 / 75
ROM - definition/design Definition A rom (2 n ) that implements a Boolean function M : [0 .. 2 n − 1] → { 0 , 1 } is defined as follows. Inputs: Address [ n − 1 : 0]( t ). Output: D out ( t ). Functionality : D out = M [ � Address � ] . M [2 n − 1 : 0] 2 n (2 n : 1) − mux Address [ n − 1 : 0] n 1 D out 23 / 75
Read-Only Memory (ROM) The contents stored in each memory cell are preset and fixed. ROMs are used to store information that should not be changed. For example, the ROM stores the program that is executed when the computer is turned on. Modern computers use non-volatile memory as ROM (such memory does allow write operations - and writing is often limited by “permissions”) 24 / 75
Random Access Memory (RAM) Hardware module that implements an array of memory cells, 1 where each memory cell stores a single bit. In each cycle, a single memory cell is accessed. 2 Two operations are supported: read and write. 3 read operation: the contents of the accessed memory is output. write operation: a new value is stored in the accessed memory cell. The number of memory cells is denoted by 2 n . 4 Each cell has a distinct address between 0 and 2 n − 1. 5 The cell to be accessed is specified by an n -bit string called 6 Address . The array of memory cells is denoted by M [2 n − 1 : 0]. Let 7 M [ i ]( t ) denote the value stored in the i th entry of the array M during clock cycle t . 25 / 75
RAM - definition Definition A ram (2 n ) is specified as follows. Inputs: Address [ n − 1 : 0]( t ) ∈ { 0 , 1 } n , D in ( t ) ∈ { 0 , 1 } , R / W ( t ) ∈ { 0 , 1 } and a clock clk . Output: D out ( t ) ∈ { 0 , 1 } . Functionality : data: array M [2 n − 1 : 0] of bits. 1 initialize: ∀ i : M [ i ] ← 0. 2 For t = 0 to ∞ do 3 D out ( t ) = M [ � Address � ]( t ). 1 For all i � = � Address � : M [ i ]( t + 1) ← M [ i ]( t ). 2 3 � D in ( t ) if R / W ( t ) = 0 M [ � Address � ]( t + 1) ← M [ � Address � ]( t ) else. 26 / 75
RAM - schematic D in Address [ n − 1 : 0] clk ram (2 n ) R/W D out Figure: A schematic of a ram (2 n ). 27 / 75
RAM -design Address [ n − 1 : 0] n decoder ( n ) 2 n sel [2 n − 1 : 0] D in sel [2 n − 1] D in sel [1] D in sel [0] 1 1 1 1 1 1 M 2 n − 1 R/W M 1 R/W M 0 R/W 1 1 1 1 1 1 D [2 n − 1] D [1] D [0] 2 n D [2 n − 1 : 0] (2 n : 1) − mux Address [ n − 1 : 0] n 1 D out 28 / 75
Memory Cell - specification Definition A single bit memory cell is defined as follows. Inputs: D in ( t ), R / W ( t ), sel ( t ), and a clock clk . Output: D out ( t ). Functionality: Assume that D out is initialized zero, i.e., D out (0) = 0. The functionality is defined according to the following cases. � D in ( t ) if sel ( t ) = 1 and R / W ( t ) = 0 D out ( t + 1) ← D out ( t ) otherwise. 29 / 75
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