Digital LLRF Technology on a TCA Platform Eugene Wu Northwestern - PowerPoint PPT Presentation

Digital LLRF Technology on a μ TCA Platform Eugene Wu Northwestern University Mentor: Tim Berenc Lee Teng Presentations August 10, 2016

Motivation  Low-level RF systems regulate the amplitude and phase of an RF cavity  Present APS LLRF systems use analog hardware  Long-term plans to upgrade to digital LLRF technology  Goal of project: evaluate microTCA based hardware for digital applications beam LO Fast LLRF Controller Cavity System Up-Converter ADCs Reference ADC IF RF Digital DAC PA Cavity IF CAV ADC Signal LO Power REV FWD CAV FWD Processing ADC Amplifier REV ADC - Field Control - Fast Tuner Algorithm Down-Converters - Slow Tuner Algorithm DAC - Calibration & Tune-Up ADC i.e., Slow - etc. i.e., vibration & Fast Tuners ADC DAC sensors CLK Slow DACs Slow ADCs 2 Eugene Wu - Lee Teng Presentations - August 2016

 micro Telecommunications Computing Architecture ( μ TCA) – Specifications-based hardware platform – Offers an ecosystem of various modules from multiple vendors – Used in high energy physics, digital LLRF, military, and telecommunications 3 Eugene Wu - Lee Teng Presentations - August 2016

Hardware Components  Vadatech AMC502 FPGA Carrier w/ Kintex-7 FPGA – 2 FPGA Mezzanine Card (FMC) Slots  D-TACQ ACQ420 Analog-to-Digital (ADC) FMC – 16-bit, Four-channel, 2 Mega-samples per second (MSPS)  D-TACQ AO400 Digital-to-Analog (DAC) FMC – 18-bit, Four-channel, 1 MSPS Eugene Wu - Lee Teng Presentations - August 2016 4

FMC0 FMC1 FPGA microTCA Backplane GbE CPU Eugene Wu - Lee Teng Presentations - August 2016 5

FPGA Design First Goal: Get ADC’s and DAC’s working Signal Processing will go here Eugene Wu - Lee Teng Presentations - August 2016 6

ADC and DAC Timing Diagrams ADC serial interface DAC serial interface Eugene Wu - Lee Teng Presentations - August 2016 7

VHDL Design  Acquired reference designs from Vadatech and D-TACQ  Modified to match hardware, wrote new DAC code – e.g., 160 FMC pins x 2, DAC serial interface  ~3600 lines of code  Synthesize design and debug  Use FPGA Integrated Logic Analyzer (ILA) to read internal signals and debug ModelSim simulation of DAC testbench VHDL testbench for simulation/debugging Eugene Wu - Lee Teng Presentations - August 2016 8

Lab Setup μ TCA chassis Function generator and oscilloscope for testing FMC Front panel connector breakout Full view of lab Eugene Wu - Lee Teng Presentations - August 2016 9

Real-time Data from FPGA Integrated Logic Analyzer Output Eugene Wu - Lee Teng Presentations - August 2016 10

ADC Data 32K Point FFT 10 kHz full-scale input on channel 1 Noise floor ~ -130 dBV 2 /Hz Harmonics were found to be due to signal source 𝑂𝑝𝑗𝑡𝑓 = 𝑂𝐺 ∗ 𝐶𝑋 ≅ 223 𝜈𝑊𝑆𝑁𝑇 𝑇𝑂𝑆 = 93 𝑒𝐶 Eugene Wu - Lee Teng Presentations - August 2016 11

DAC Output FFT of DAC Output (Stanford Research Systems SR785) ADC DAC Input Output Eugene Wu - Lee Teng Presentations - August 2016 12

Summary  Successfully demonstrated use of ADC and DAC modules on a microTCA FMC carrier for baseband signal acquisition  Future work – Past application of baseband signal processing was for AM/PM noise suppression in APS storage ring RF systems (previous Lee Teng project using proprietary National Instruments hardware) – Intent is to migrate noise suppression algorithm to microTCA – Possibly start on signal processing next week – Ultimately need to transition into intermediate frequency signals for full digital LLRF Eugene Wu - Lee Teng Presentations - August 2016 13