Development of readout test system for prototype ASIC of pixel - PowerPoint PPT Presentation

Kuno and Yamanaka Group Year-End Presentation 2017 Development of readout test system 
 for prototype ASIC 
 of pixel detector for ATLAS upgrade ATLAS アップグレード用ピクセル検出器の 
 プロトタイプ ASIC 読み出し試験システムの開発 28/12/2017 Osaka University M2 Yasunori Sawada

Overview 1.ATLAS Experiment 2.HL-LHC ATLAS Pixel 3.Pixel ASIC 4.ASIC Readout system 5.Summary Kuno and Yamanaka Group Year-End Presentation 2017 2

1.ATLAS Experiment - HL-LHC • HL-LHC ATLAS - 2026~ • Energy - 14 TeV • Luminosity - ~7.5 × 10 34 cm -2 s -1 Kuno and Yamanaka Group Year-End Presentation 2017 3

2.HL-LHC ATLAS Pixel detector Detect charged particles Semiconductor Sensor h + e - e - h + Si e - h + e - h + ASIC Digitization of signal (Application specific integrated circuit) & some functions 0111011011111…. Data processing, FPGA Board PC Interface …etc (Field programmable gate array) Kuno and Yamanaka Group Year-End Presentation 2017 4

2.HL-LHC ATLAS Pixel detector • Pixel hit rate in HL-LHC ~ average 100-150 • Requirements • Matrix size : 400 × 384 • Pixel pitch : 50 × 50 μ m 2 • Trigger rate : 
 1 MHz (w/ <35 μ s latency) → ~2.6 Gbps ~100 Hits/event × 1 MHz × 26 bit/Hit → Development ASIC, RD53 Collaboration Kuno and Yamanaka Group Year-End Presentation 2017 5

3.Pixel ASIC - RD53A • Prototype ASIC RD53A 
 - Half size of production • ATLAS Japan group 
 Demand for Data acquisition system - Radiation tolerance test 
 development ! - Test beam • Required performance 
 - Readout bandwidth : ~5 Gbps/chip Kuno and Yamanaka Group Year-End Presentation 2017 6

4.ASIC Readout System Development milestones { 1. FE-I4 Readout system using Ethernet 2. FE-I4 Readout system using PCI Express 
 • FE-I4 - Currently used ASIC in ATLAS Pixel 3. RD53A Readout system using PCI Express 
 High speed Xilinx KC705 Evaluation Board Kuno and Yamanaka Group Year-End Presentation 2017 7

4.ASIC Readout System - Ethernet 1. FE-I4 Readout system using Ethernet Computer < 1Gbps Ethernet (UDP/IP, TCP/IP) SiTCP FIFO Trigger &Command 8Bit → 10Bit Clock Serial → Parallel 80 MHz 160 Mbps 40 MHz Readout ASIC • Implemented in commercially available board ! • Not support 5 Gbps readout, but enough for FE-I4 x4~x6(?) Kuno and Yamanaka Group Year-End Presentation 2017 8

4.ASIC Readout System - Ethernet 1. FE-I4 Readout system using Ethernet • Operation Test • Tuning of thresholds for Hit • Tuning of ToT (like ADC Value) to each pixel # Pixels # Pixels # pixels 200 Target ToT : 10 for 20000e Target threshold : 3600e 250 180 Blue : Before tuning Blue : Before tuning Red : After tuning 160 Red : After tuning 200 140 120 150 100 80 100 60 40 50 20 0 0 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 0 2 4 6 8 10 12 14 16 Threshold [e] ToT Threshold [e] ToT Kuno and Yamanaka Group Year-End Presentation 2017 9

PCI Express 4.ASIC Readout System - PCIe 2. FE-I4 Readout system using PCI Express FE ASIC DDR3 Memory Decoder & Encoder & Deserializer Trigger Serializer RxBridge DDR3 Controller Unit TxCore RxCore Wishbone Bus DMA Wishbone Bus Wishbone express core DMA Controller 7 Series FPGAs Integrated Block for PCI Send command Readout Data & trigger Kuno and Yamanaka Group Year-End Presentation 2017 10

4.ASIC Readout System - PCIe 2. FE-I4 Readout system using PCI Express • Direct Memory Access • PCI Express Program Memory READ ~ 750MB/s WRITE READ PCI WRITE ~ 700MB/s Express Memory Data block size [KByte] Kuno and Yamanaka Group Year-End Presentation 2017 11

5.Summary • FE-I4 Readout system on KC705 was developed ! • High speed DAQ system 
 → Transfer speed performance between FPGA and PC was achieved ! ~750MB/s (READ) 
 • Future • Complete DAQ system 
 + Understanding data transfer performance 
 + Adapt to RD53A Kuno and Yamanaka Group Year-End Presentation 2017 12

Additional Slides

Development components Signal Pixel Assembly Evaluation FPGA Board transmission test Group FPGA Firmware DAQ Software Characteristic test DAQ Group Frontend ASIC Zynq DAQ System Kuno and Yamanaka Group Year-End Presentation 2017 14

2.HL-LHC ATLAS Pixel detector Pixel detector in ATLAS Semiconductor Sensor Detect charged particles ASIC (Application specific integrated circuit Digitization of signal & some functions Kuno and Yamanaka Group Year-End Presentation 2017 15

Hit rate & Data rate Kuno and Yamanaka Group Year-End Presentation 2017 16

5 Gbps / chip serial output • Estimation of requirement 5 Gbps/chip • Hit occupancy / FE / event : ~200 • Data frame length per 1 Hit : 26 bit • Trigger rate : 1 MHz 1 MHz = ~5 Gbps 200 Hits/event × 26 bit/Hit × (~650 MB/s) Kuno and Yamanaka Group Year-End Presentation 2017 17

Pixel Sensor readout ASIC prototype (RD53A) ATLAS 及び CMS のフェーズ２アップグレードに向けて開発されている 
 • FE-I4 RD53A 50x250 um 2 50x50 um 2 (25x100) um 2 ) Cell Size 次世代読み出し ASIC 400x192 Pixel Matrix 80x336 デモンストレータ → 性能評価などが行われている • 20.0x2.8 mm 2 18.2x19.0 mm 2 Chip Size FPGA に実装可能なエミュレータが開発されている • ~ 1 G Transistor ~80 M Input Rate 160 Mbps 40 Mbps ~5 Gbps Output Rate 160 Mbps 1 MHz (L0) Trigger Rate 200 kHz > 500 Mrad Radiation 300 Mrad 65 nm CMOS Process 130 nm 150 um Thickness 150 um Kuno and Yamanaka Group Year-End Presentation 2017 18

Analog pixel schematic diagram ToT Tuning Threshold Tuning Pixel threshold Global threshold Charge Injection Q=C × V cal Kuno and Yamanaka Group Year-End Presentation 2017 19

4.ASIC Readout System 1. FE-I4 Readout system using Ethernet • Operation Test - Threshold Tuning • Set Threshold for Hit judgment for each pixel • Adjust the feedback current for discriminator to tune target threshold • Result was obtained by measurement. Target threshold : 3,600e Hit occupancy # Pixels 200 # Pixels thres_after_0 thres_after_0 S-curve 180 Entries Entries 672 672 160 Mean 3596 Mean 3596 RMS RMS 60.61 60.61 140 120 100 80 60 40 20 0 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 Threshold [e] Threshold [e] PlsrDAC ~ Feedback Current Kuno and Yamanaka Group Year-End Presentation 2017 20

4.ASIC Readout System 1. FE-I4 Readout system using Ethernet • Operation Test - ToT(Time over threshold) Tuning • ToT is determined with input charge amounts • Adjust the feedback current for preamp 
 to tune target ToT. Target ToT : 10@20,000e ∝ Energy # Pixels # Pixels tot_after_0 tot_after_0 250 Entries Entries 672 672 10.02 10.02 Mean Mean RMS 0.5785 RMS 0.5785 200 150 Threshold 100 50 0 0 2 4 6 8 10 12 14 16 Time ToT ToT ToT Kuno and Yamanaka Group Year-End Presentation 2017 21

PCI Express 4.ASIC Readout System - PCIe 2. FE-I4 Readout system using PCI Express FE ASIC DDR3 Memory Decoder & Encoder & Deserializer Trigger Serializer RxBridge DDR3 Controller Unit TxCore RxCore Wishbone Bus DMA Wishbone Bus Wishbone express core DMA Controller 7 Series FPGAs Integrated Block for PCI Send command Readout Data & trigger Kuno and Yamanaka Group Year-End Presentation 2017 22

DMA Operation time • Operation Time of DMA transfer 
 obtained by gettimeoday() 
 Left : Transfer time + Memory Allocation Time + a 
 Right : Memory Allocation Time + a Trials:100 Trials:100 Kuno and Yamanaka Group Year-End Presentation 2017 23