CLB: Current status and development on CLBv2 in Valencia David - PowerPoint PPT Presentation

CLB: Current status and development on CLBv2 in Valencia David Calvo IFIC (CSIC – Universidad de Valencia) Marseille 30 January 2013

TDC: DESIGN KC705 LVDS Output 48 bits ( Resolution: 1ns ) Input DESERIALIZER Signal FIFO RECOVERY UNIT 8 bits 32 bits 8 bits Header Time Stamp Pulse width

TDC: 31 CHANNELS Enable Interface KC705 Ch.1 LVDS SIGNAL DISTRIBUTION Ch.1 Input MULTIPLEXER Signal Ch.2 Output (48 bits) PC Ch.31 Ch.31 3

TDC: TEST Enable Interface KC705 Ch.1 Well-known pattern ML605 LVDS SIGNAL DISTRIBUTION Ch.1 Input MULTIPLEXER Signal Ch.2 Output (48 bits) PC Ch.31 Ch.31 4

TDC: PATTERNS TO TEST CHANNEL 1 CHANNEL 2 5 Jitter = 0.3 ns

TDC: PATTERN TO TEST Patterns replicated 250 times 1000 pulses x channel CHANNEL 1 CHANNEL 2 6

TDC: RESULT CHANNEL 1 CHANNEL 2 Pulse width counts counts ns ns 7

TDC: RESULT CHANNEL 2 CHANNEL 1 Time between pulses counts counts ns ns 8

LM32 DEVELOPMENTS IN VALENCIA • LM32 SOC with several wishbone slaves (32 bits bus): o BRAM o UART o TIMER o I2C0 Nanobeacon o I2C1 Temperature and Humidity sensor (DIGIPICCO) o GPIO Xilinx Data Spartan-6 Wishbone shared bus (32 bits) Nano Beacon Debug LEDs 2 nd CPU TIMER GPIO UART I2C0 I2C1 B RAM LM32 Temp and RS-232 HYPERTERMINAL Humidity Sensor

LM32 DEVELOPMENTS IN VALENCIA Time Slice Start IP/UDP Packet Buffer 31 TDCs Start Time Slice UTC & Stream Selector (IPMUX) Offset counter since 31 PMTs Fifo TDC0 RxPort 1 RxPacket Rx_mac2buf Rx_buf2data Rx Stream RxPort 2 Buffer Select 64KB TDC Fifo 30 State Machine Flags RxPort_m Management S & Control Management Pause Frame & Config. Hydrophone Fifo ADC TxPort 1 TxPacket Tx_data2buf Tx_pkt2mac Tx Stream TxPort 2 Buffer Select 32KB Management Flags TxPort_m S S & Control Nano M M Beacon M S WB Crossbar M M (1x7) M M M Debug M 2 nd CPU S S S S S M M SPI I2C I2C GPIO S UART LEDs Xilinx MEM WB Crossbar M S LM32 S (3x2) M Kintex-7 Data UTC time & Clock (PPS, 125 MHz) Compass Debug Temp Tilt SPI Control Point to Point interconnection RS232 Flash Wishbone bus

NEXT STEPS IN VALENCIA (I) Time Slice Start IP/UDP Packet Buffer 31 TDCs Start Time Slice UTC & Stream Selector (IPMUX) Offset counter since 31 PMTs Fifo TDC0 RxPort 1 RxPacket Rx_mac2buf Rx_buf2data Rx Stream RxPort 2 Buffer Select 64KB TDC Fifo 30 State Machine Flags RxPort_m Management S & Control Management Pause Frame & Config. Hydrophone Fifo ADC TxPort 1 TxPacket Tx_data2buf Tx_pkt2mac Tx Stream TxPort 2 Buffer Select 32KB Management Flags TxPort_m S S & Control Nano M M Beacon M S WB Crossbar M M (1x7) M M M Debug M 2 nd CPU S S S S S M M SPI I2C I2C GPIO S UART LEDs Xilinx MEM WB Crossbar M S LM32 S (3x2) M Kintex-7 Data UTC time & Clock (PPS, 125 MHz) Compass Debug Temp Tilt SPI Control Point to Point interconnection RS232 Flash Wishbone bus

NEXT STEPS IN VALENCIA (II) Time Slice Start IP/UDP Packet Buffer 31 TDCs Start Time Slice UTC & Stream Selector (IPMUX) Offset counter since 31 PMTs Fifo TDC0 RxPort 1 RxPacket Rx_mac2buf Rx_buf2data Rx Stream RxPort 2 Buffer Select 64KB TDC Fifo 30 State Machine Flags RxPort_m Management S & Control Management Pause Frame & Config. Hydrophone Fifo ADC TxPort 1 TxPacket Tx_data2buf Tx_pkt2mac Tx Stream TxPort 2 Buffer Select 32KB Management Flags TxPort_m S S & Control Nano M M Beacon M S WB Crossbar M M (1x7) M M M Debug M 2 nd CPU S S S S S M M SPI I2C I2C GPIO S UART LEDs Xilinx MEM WB Crossbar M S LM32 S (3x2) M Kintex-7 Data UTC time & Clock (PPS, 125 MHz) Compass Debug Temp Tilt SPI Control Point to Point interconnection RS232 Flash Wishbone bus

NEXT STEPS IN VALENCIA (III) Time Slice Start IP/UDP Packet Buffer 31 TDCs Start Time Slice UTC & Stream Selector (IPMUX) Offset counter since 31 PMTs Fifo TDC0 RxPort 1 RxPacket Rx_mac2buf Rx_buf2data Rx Stream RxPort 2 Buffer Select 64KB TDC Fifo 30 State Machine Flags RxPort_m Management S & Control Management Pause Frame & Config. Hydrophone Fifo ADC TxPort 1 TxPacket Tx_data2buf Tx_pkt2mac Tx Stream TxPort 2 Buffer Select 32KB Management Flags TxPort_m S S & Control Nano M M Beacon M S WB Crossbar M M (1x7) M M M Debug M 2 nd CPU S S S S S M M SPI I2C I2C GPIO S UART LEDs Xilinx MEM WB Crossbar M S LM32 S (3x2) M Kintex-7 Data UTC time & Clock (PPS, 125 MHz) Compass Debug Temp Tilt SPI Control Point to Point interconnection RS232 Flash Wishbone bus

NEXT STEEPS IN VALENCIA (IV) Implement reconfigurability: A.- To use the multiboot capabilities of the KINTEX B.- To be able to write on the SPI FLASH with the LM32 Xilinx Data Kintex KC705 Wishbone shared bus (32 bits) 2 nd CPU SPI LM32 Multiboot image – upgraded image SPI (read /write) QFLASH Golden Image (read only) MEMORY

THANKS FOR YOUR ATTENTION!

LM32 developments in Valencia Time Slice Start IP/UDP Packet Buffer 31 TDCs Start Time Slice UTC & Stream Selector (IPMUX) Offset counter since 31 PMTs Fifo TDC0 RxPort 1 RxPacket Rx_mac2buf Rx_buf2data Rx Stream RxPort 2 Buffer Select 64KB TDC Fifo 30 State Machine Flags RxPort_m Management S & Control Management Pause Frame & Config. Hydrophone Fifo ADC TxPort 1 TxPacket Tx_data2buf Tx_pkt2mac Tx Stream TxPort 2 Buffer Select 32KB Management Flags TxPort_m S S & Control Nano M M Beacon M S WB Crossbar M M (1x7) M M M Debug M 2 nd CPU S S S S S M M SPI I2C I2C GPIO S UART LEDs Xilinx MEM WB Crossbar M S LM32 S (3x2) M Kintex-7 Data UTC time & Clock (PPS, 125 MHz) Compass Debug Temp Tilt SPI Control Point to Point interconnection RS232 Flash Wishbone bus