Development of monolithic sensors for high energy physics in - PowerPoint PPT Presentation

Argonne, September, 2018 Development of monolithic sensors for high energy physics in commercial CMOS technologies W. Snoeys, CERN p-ALPIDE3 chip: 200 MeV p at PSI

Acknowledgements § The workshop organizers § T. Kugathasan, G. Aglieri, H. Pernegger, L. Musa, P. Riedler § G. Anelli, F. Anghinolfi, P. Aspell, R. Ballabriga, S. Bonacini, M. Campbell, J. Christiansen, R. De Oliveira, F. Faccio, P. Farthouat, E. Heijne, P. Jarron, J. Kaplon, K. Kloukinas, A. Kluge, T. Kugathashan, X. Llopart, A. Marchioro, S. Michelis, P. Moreira, K. Wyllie, M. Mager, M. Keil, D. Kim, A. Dorokhov, A. Collu, C. Gao, P. Yang, X. Sun, H. Hillemanns, S. Hristozkov, A. Junique, M. Kofarago, M. Keil, A. Lattuca, M. Lupi, C. Marin Tobon, D. Marras, M. Mager, P. Martinengo, G. Mazza, H. Mugnier, H. Pham, J. Rousset, F. Reidt, P. Riedler, J. Van Hoorne, P. Yang, D. Gajanana , A. Sharma, B. Blochet, C. Sbarra, C. Solans Sanchez, C. Riegel, C. Buttar, D. Michael Schaefer, D. Maneuski, I. Berdalovic, K. Moustakas, M. Dalla, N. Wermes, N. Egidos Plaja, R. Bates, R. Cardella, T. Wang, T. Hemperek, T. Hirono, W. Wong, G. Iacobucci, M. Barbero, P. Pangaud, A. Habib, S. Bhat, I. Peric, R. Casanova, S. Grinstein, Y. Degerli, F. Guilloux, P. Schwemling, M. Muenker… and other colleagues from CERN, the ALICE ITS upgrade and ATLAS ITk 2

CMOS Monolithic Active Pixel Sensors or CMOS MAPS CMOS MAPS have changed the imaging § world, reaching: less than 1 e - noise § (cfr S. Kawahito, PIXEL 2012) > 40 Mpixels § Wafer scale integration § Wafer stacking § … § In High Energy Physics silicon has become § the standard in tracking applications both for sensor and readout … and now CMOS MAPS make their § way in High Energy Physics ! Backside Illuminated 8M Pixel Stacked Imaging Sensor Note: advanced 3D assembly techniques § S. Sugawa et al. Sony Corp. make distinction between hybrid ISSCC 2013 (separate sensor and readout chip) and monolithic more vague 3 walter.snoeys@cern.ch

Monolithic sensors in HEP move into mainstream technology ALPIDE in ALICE MIMOSA28 (ULTIMATE) in STAR First MAPS in HEP with sparse IPHC Strasbourg readout similar to hybrid sensors First MAPS system in HEP Quadruple well 0.18 μm CMOS Twin well 0.35 μm CMOS § Integration time <10 μs § Integration time 190 μs § Reverse bias but no full depletion § No reverse bias -> NIEL few -> NIEL ~10 14 1 MeV n eq /cm 2 10 12 1 MeV n eq /cm 2 DEPFET in Belle § Rolling shutter readout Commercial deep submicron CMOS technology evolved “naturally” towards Very high tolerance to ionizing radiation (some caveats, see below) § Availability of substrates compatible with particle detection § 4 walter.snoeys@cern.ch

ALICE ITS upgrade See also L. Greiner’s presentation Sensor chip requirements Parameter Inner Barrel Outer Barrel Chip size (mm x mm) 15 x 30 Chip thickness ( µ m) 50 100 Spatial resolution ( µ m) 5 10 (5) Motivation Detection efficiency > 99% Fake hit rate < 10 -5 evt -1 pixel -1 (ALPIDE << 10 -5 ) • 3x better impact parameter resolution Integration time ( µ s) < 30 (< 10) • Better tracking efficiency and Power density (mW/cm 2 ) < 300 (~35) < 100 (~20) momentum resolution at low pT TID radiation hardness (krad) (**) 2700 100 • Faster readout NIEL radiation hardness (1 MeV n eq /cm 2 ) 1.7 x 10 13 1.7 x 10 12 (**) • Fast removal and insertion Readout rate, Pb-Pb interactions (kHz) 100 Hit Density, Pb-Pb interactions (cm -2 ) 18.6 2.8 Technical Design Report for the (*) In color: ALPIDE performance figure where above requirements Upgrade of the ALICE Inner Tracking System (**) 10x radiation load integrated over approved program (~ 6 years) J. Phys. G 41 (2014) 087002 CERN-LHCC-2013-024 ; ALICE-TDR-017 Thin sensors (50 μm), high granularity (~30 x 30 μm 2 ), large area (10 m 2 ) Monolithic Active moderate radiation (TID 2.7 Mrad & NIEL 1.7 10 13 1 MeV n eq /cm 2 ) Pixel Sensors 5

Standard Pixel Sensor imaging Process (TowerJazz) CMOS 180nm 3 nm thin gate oxide, 6 metal layers SUB SUB AVDD IRESET VRESET PIX_IN pwell nwell NWELL NMOS PMOS deep pwell deep pwell DIODE TRANSISTOR TRANSISTOR epitaxial layer PWELL PWELL NWELL p substrate N A ~ 10 16 cm -3 DEEP PWELL Not to scale Spacing h e Diameter C) e PMOS Reset VRESET_P h h N A ~ 10 13 cm -3 e e M0b h Epitaxial Layer P- Substrate P++ N A ~ 10 18 cm -3 IRESET Collection electrode Not to scale AVSS SUB • High-resistivity (> 1k Ω cm) p-type epitaxial layer (18 µ m to 30 µ m) on p-type substrate • Deep PWELL shielding NWELL allowing PMOS transistors (full CMOS within active area) • Small n-well diode (2 µ m diameter), ~100 times smaller than pixel and reverse substrate bias => low capacitance (2fF) => large S/N => better analog performance at lower power. 6

ALPIDE 1024 pixel columns VDDA 20nA IBIAS Readout (zero suppression) Readout (zero suppression) Readout (zero suppression) Readout (zero suppression) IDB 0.5nA M0 M7 C source ITHR source M4 Cs PIX_IN 512 rows OUT_D M1 VCASN M5 VCASP M6 M2 M8 OUT_A curfeed C OUT_A M3 C curfeed Bias, Readout, Control AMP COMP GNDA Front end (40 nW, continuously active) Matrix THR D. Kim et al. TWEPP 2015, G. Aglieri et al. NIM A 845 (2017) 583-587 DOI 10.1088/1748-0221/11/02/C02042 29 µ m x 27 µ m pixel pitch • Analog power ~ (Q/C) -2 NIM A 731 (2013) 125 In pixel amplification and discrimination and 3 data • • registers C(sensor+circuit) < 5 fF, Q/C ~ 50 mV in ALPIDE • Global shutter, triggered or continuous readout • Used with increased current for ATLAS development • Zero suppressed readout, no hits no power • Design team: G. Aglieri, C. Cavicchioli, Y. Degerli, C. Flouzat, D. Gajanana, C. Gao, F. Guilloux, S. Hristozkov, D. Kim, T. Kugathasan, A. Lattuca, S. Lee, M. Lupi, D. Marras, C.A. Marin Tobon, G. Mazza, H. Mugnier, J. Rousset, G. Usai, A. Dorokhov, H. Pham, P. Yang, W. Snoeys (Institutes: CERN, INFN, CCNU, YONSEI, NIKHEF, IRFU, IPHC) and comparable team for test 1 MPW run and 5 engineering runs 2012-2016, production 2017-2018

ALPIDE Layout features Pixel layout Collection Diode Priority encoder Priority encoder Front End 26.88 μm Matrix (detail) Digital Pixel Section 9.66μm 19.58 μm 29.24 μm Matrix - Pixels and Priority Encoders Soldering pads Analog DACs over circuits 1.208 mm Periphery (detail) Digital Periphery Sea of gates SRAM blocks Regular pads + Custom blocks 8

ALPIDE – Some Results Charge threshold and Noise Noise Map noise in electrons Noise Noise Threshold MAP thresholds in electrons Thresholds Threshold 9

Detection Efficiency and Fake Hit Rate − 4 100 10 Detection Efficiency (%) NIEL/TID Fake-Hit Rate/Pixel/Event − V BB =-3V 5 10 98 − 6 10 96 Efficiency Fake-hit Rate @ V =-3V BB W7-R10 Non Irradiated − W7-R7 Non Irradiated 7 10 94 W7-R17 TID Irradiated, 206 krad W7-R5 TID Irradiated, 205 krad − 8 W7-R38 TID Irradiated, 462 krad 10 92 W7-R41 TID Irradiated, 509 krad 3 W8-R5 NIEL, 1.7e+13 1MeV n / cm eq − 3 9 W8-R7 NIEL, 1.7e+13 1MeV n / cm 10 eq 90 − 10 10 88 Sensitivity Limit 10 Pixels masked − 11 10 86 − 12 10 100 100 200 200 300 300 400 400 500 500 - Threshold (e ) Large operational margin with only 10 masked pixels (0.002%) • Chip-to-chip fluctuations negligible • Non-irradiated and NIEL/TID chips show similar performance • Sufficient operational margin after 10x lifetime NIEL dose • 10

ALPIDE & ITS Upgrade status Wafer probe testing Single chips after thinning & dicing Threshold scan outer Barrel Module (14 chips) 1400 wafers produced Inner Barrel Module (9 chips) Outer Barrel Stave (~100 M pixels) 11

Dose Fluence Requirements for HEP (Mgy) (10 16 1MeVn eq /cm 2 ) ALICE ITS 0.01 10 -3 Radiation tolerance § 0.1 … 0.3 LHC 1 Ionizing radiation § HL-LHC 3ab -1 5 1.5 Non-ionizing radiation § (displacement damage) FCC 10-350 3-100 Circuit typically more sensitive to ionizing radiation, sensor to non-ionizing radiation § Single particle hits instead of continuously collected signal in visible imaging § Sparse images < or << 1% pixels hit per event § Near 100% efficiency, full CMOS in-pixel needed § Position resolution (~μm) § Low power consumption is the key for low mass § Now tens of mW/cm 2 for silicon trackers and hundreds of mW/cm 2 for pixels § Even with enhanced detector functionality for upgrades, power consumption cannot § increase too much because of the material penalty More bandwidth § Time resolution § Time stamping ~ 25 ns or even lower, ... much lower (10s of ps) § 12 walter.snoeys@cern.ch