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Dependability and Security Challenges Dependability and Security Challenges in Emerging Technologies in Emerging Technologies Jacob A. Abraham Jacob A. Abraham University of Texas at Austin University of Texas at Austin Workshop Panel Workshop Panel June 28, 2007 June 28, 2007 1 JAA 6/28/2007 JAA 6/28/2007

Nanoscale CMOS Trends Moore's Law 2 JAA 6/28/2007 JAA 6/28/2007

Process Variations Source: Intel 3 JAA 6/28/2007 JAA 6/28/2007

Nanoscale CMOS Example Fin-FETs 4 JAA 6/28/2007 JAA 6/28/2007

Effects on Circuits and Systems Experiments on chips today show that running some chips at rated speeds produce errors Correct operation when running at normal speeds Resistive opens (possible in copper interconnect) cause delay defects Crosstalk effects could also cause errors As technology scales down, chips in the future prone to erroneous operation due to: Process variations (soft errors) Increasing defects (today's memories are an example) 5 JAA 6/28/2007 JAA 6/28/2007

New Nano Systems Carbon Nanotubes Courtesy: IBM 6 JAA 6/28/2007 JAA 6/28/2007

New Nano Systems Quantum Devices Dot occupied Inter-dot by Electron Barriers Dot unoccupied Outer Barriers Quantum Cellular Automata 1 1 QCA Wire “1” “0” Stable 1 0 Unstable QCA Inverter 7 JAA 6/28/2007 JAA 6/28/2007

Dealing with Errors Redundancy Hardware (duplication/retry, triplication) Time (recomputation) Basic ideas in dealing with errors are not new Moore and Shannon, 1956: “Reliable Circuits Using Less Reliable Relays” von Neumann, 1956: “Probabilistic Logic and the Synthesis of Reliable Organisms from Unreliable Components” Self-checking circuits (1970s) Algorithm-based fault tolerance (1980s) Software-based checks (control flow checks, etc.) (1980s) 8 JAA 6/28/2007 JAA 6/28/2007

Redundancy at Different Levels Switch (Circuit) level Module level Functional Inputs Outputs Module Self Checking Error Checker Voter System 9 JAA 6/28/2007 JAA 6/28/2007

Protecting Computations at the System Level B jk Row 1 3 2 4 Checksum Algorithm-Based 1 Fault Tolerance 2 A ij 3 Overhead decreases as system gets larger! 4 Column Checksum 10 JAA 6/28/2007 JAA 6/28/2007

CEDA: Control-flow Error Detection through Assertions (Integrated with GCC) S: global runtime signature register – updated at the beginning and end of each node – each update either an XOR or an AND operation – op. performed based on the program graph properties Se: expected value of S at each point in the program Se = 0101 - calculated at compile time S = S XOR 0110 br S != 0011 err Check point: S is checked against its expected value - detects CFE if one occurred Se = 0011 - not required inside every node S = S XOR 1011 Se = 1000 Node signature: expected value of S inside a node Node exit signature: expected value of S immediately after exiting a node 11 JAA 6/28/2007 JAA 6/28/2007

Dealing with Faults Increasing possibility of defects Defect tolerance key for yield Want system to start in a good state Cannot produce cost-effective DRAMS without replacing faulty cells with spares However, sparing cells is much more difficult for logic (very high cost for multiplexers, routing) 12 JAA 6/28/2007 JAA 6/28/2007

Defect Tolerance in Carbon Nanotube Circuits Source: Mitra 13 JAA 6/28/2007 JAA 6/28/2007

What are some of the characteristics of future products? Low-cost consumer products 1 400 1 200 High frequency, MS-SOC high resolution 1 000 Market Size (B$ ） Contribution to the signals SoC Market Size 800 System service 600 SoC World Wide (what matters is Market Semiconducto 400 what customer Size r Market Size sees) 200 0 Regulations '93 '95 '97 '99 '03 '05 '07 '09 '11 91 01 19 20 14 JAA 6/28/2007 JAA 6/28/2007

Objective of dependability Guarantee that the system meets customer or regulatory specifications Need not check directly for the specifications This is becoming impossible to do with low cost Only solution for systems of the future is indirect checks from which the specifications can be inferred accurately LNA IIP3 1.5 1 0.5 Detector Output Measured IIP3 [dBm] 0 -0.5 10M Samples per Second -1 -1.5 IIP3 y=x ref line -2 Third harmonic of -2.5 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 Predicted IIP3 [dBm] 940 MHz RF system deduced from 10 MS/sec detector output 15 JAA 6/28/2007 JAA 6/28/2007

Conclusions Need to deal with soft errors (due to variations, etc.) Detection and correction techniques Tolerate defects in manufacture Lots of devices, but efficiently using them is key Level to apply solutions? Usually higher levels are better May find good solutions at low levels, too Can utilize many “old” techniques Need to look for “new” techniques 16 JAA 6/28/2007 JAA 6/28/2007