CS3330: PIPE 4 1700 5 F --- F --- --- 8 9 9 8 1700 F --- --- F F 0x2 3 9 800 --- 800 from incremented PC no-op value (“bubble”)? should we send no-op value — 0xF MUX rA fetch/decode logic — bubble or not 3 to instruction memory should we stall? MUX F PC fetch/fetch logic — advance or not 2 R[9] written during cycle 3; read during cycle 4 execute/writeback decode/execute fetch/decode 8 2500 6 900 F 1 next R[dstE] // // initially %r8 = 800, add 2 ADD ADD 0xF split R[srcB] R[srcA] next R[dstM] addq %r8, %r9 dstE dstM srcB srcA register fjle Mem. Instr. PC Last time: data hazard stall %r9 = 900, etc. // hardware stalls twice F next R[dstE] 0x2* 2 9 8 0x2* 1 0x0 0 dstE 4 addq %r9, %r8 rB rA PC cycle dstE next R[dstE] rB rA fetch R[srcA] R[srcB] dstE R[srcA] R[srcB] dstE
preview: HCL2D shortcuts i dstM srcB srcA register fjle Mem. Instr. PC SEQ + pipeline registers 6 for ret except jCC/ret to PC c g next R[dstM] o l to reg c i g o l c i g o l c dstE next R[dstE] g l for ret except jCC/ret to PC c i g o l to reg c i g o c R[srcA] i g o l c i g o l Stat ZF/SF Mem. Data R[srcB] i o HCL2D provides these MUXes for you — for every R[srcA] g o l c i g o l Stat ZF/SF Mem. Data R[srcB] next R[dstE] c next R[dstM] dstE dstM srcB srcA register fjle Mem. Instr. PC SEQ + pipeline registers 5 more Thursday/next Tuesday controlled by “bubble” and “stall” signals register bank i l l Instr. Stat ZF/SF Mem. Data R[srcB] R[srcA] next R[dstE] next R[dstM] dstE dstM srcB srcA register fjle Mem. PC o SEQ + pipeline registers 6 for ret except jCC/ret to PC c i g o l to reg c i g 6
SEQ + pipeline registers writing 7 don’t want to halt until everything else is done get value updated for prior instruction read/write in same stage avoids data hazards writeback — writing register fjle, writing Stat register memory — memory read/write execute — computation, condition code reading and fetch — instruction memory, most PC computation decode — reading register fjle fetch — instruction memory, most PC computation Stages 6 for ret except jCC/ret Stages decode — reading register fjle PC decode — reading register fjle don’t want to halt until everything else is done get value updated for prior instruction read/write in same stage avoids data hazards memory — memory read/write writing execute — computation, condition code reading and fetch — instruction memory, most PC computation writing Stages 7 don’t want to halt until everything else is done get value updated for prior instruction read/write in same stage avoids data hazards writeback — writing register fjle, writing Stat register memory — memory read/write to PC c i next R[dstE] Stat ZF/SF Mem. Data R[srcB] R[srcA] next R[dstM] g dstE dstM srcB srcA register fjle Mem. Instr. l 7 o o o l to reg c i g l g c i g o l c i execute — computation, condition code reading and writeback — writing register fjle, writing Stat register
pipeline register naming convention memory read/write logic … to instr. mem 9 simple PC update: code last week’s lab… icode = i10bytes[0..4]; f_pc = [ icode == ADD || ...: F_pc + 2; icode == IRMOVQ || ...: F_pc + 10; ... ]; 10 data memory +2 address data input data output is read? is write? icode from instr. mem from instr. mem. +10 icode (from instr. mem) PC 0xF Instr. Mem. register fjle srcA srcB dstM dstE next R[dstM] next R[dstE] R[srcA] R[srcB] split ADD convert icode ADD add 2 f_rA D_rA d_dstE E_dstE F_pc f_pc 8 normal PC update: logic PC MUX 11
memory read/write logic memory read/write: PIPE code mem. 11 memory read/write: SEQ code icode = i10bytes[4..8]; mem_readbit = [ icode == MRMOVQ || ...: 1; 0; ]; 12 f_icode = i10bytes[4..8]; from register fD { /* and dE and eM and mW */ icode : 4 = NOP; } d_icode = D_icode ... e_icode = E_icode; mem_readbit = [ M_icode == IMRMOVQ || ...: 1; 0; ]; instr. from instr. mem data memory instr. address data input data output is read? is write? icode from instr. mem from mem. icode 11 memory read/write logic data memory address data input data output is read? is write? 13
memory read/write: PIPE code icode f_icode = i10bytes[4..8]; stage pushq rA fetch PC update decode execute memory write back PC icode data and control hazards icode icode icode, rA, rB icode icode icode icode, valA, valB icode, valA icode icode icode, valA, valE 15 pushq pipeline registers what instruction to run next? examples: register fD { /* and dE and eM and mW */ icode : 4 = NOP; } d_icode = D_icode ... e_icode = E_icode; mem_readbit = [ M_icode == IMRMOVQ || ...: 1; 0; ]; 13 in general will always pass icode in pipeline registers control logic (often not drawn) will use it 16 two exceptions (share between instructions): register number selection e.g. decode stage: send to execute ( d_icode , …) e.g. decode stage: get from fetch ( D_icode , …) use only prior stage’s outputs coding pipeline stages 14 ALU input selection stalling icode : ifun ← M 1 [ PC ] valP ← PC + 2 PC ← valP set only inputs for next stage valA ← R [ rA ] valB ← R [% rsp ] valE ← valB − 8 M [ valE ] ← valA
pushq pipeline registers icode 16 icode, valA, valE icode icode icode, valA icode, valA, valB icode icode icode icode, rA, rB icode icode stage icode PC write back memory execute decode PC update stage pushq rA stage pushq pipeline registers 16 addq pipeline registers addq rA, rB icode icode, rB but will make handling data hazards easier redundant with rB + icode icode, dstE, valE icode, dstE, valE icode, dstE, valA, valB icode, rA, rB icode, rB, valE icode, rB, valE icode, rB, valA, valB icode, rB icode, rB icode, rA, rB fetch icode icode icode icode PC write back memory execute rB dstE decode PC update icode, valA, valE fetch icode icode, rA, rB stage pushq pipeline registers 16 icode, valA icode icode icode, valA icode, valA, valB icode icode icode icode fetch icode icode icode PC write back memory execute decode PC update fetch pushq rA pushq rA icode, valA, valE PC update write back icode, valA, valB icode icode icode icode, rA, rB icode icode icode icode PC 17 decode execute memory icode : ifun ← M 1 [ PC ] icode : ifun ← M 1 [ PC ] valP ← PC + 2 valP ← PC + 2 PC ← valP PC ← valP valA ← R [ rA ] valA ← R [ rA ] valB ← R [% rsp ] valB ← R [% rsp ] valE ← valB − 8 valE ← valB − 8 M [ valE ] ← valA M [ valE ] ← valA icode : ifun ← M 1 [ PC ] icode : ifun ← M 1 [ PC ] valP ← PC + 2 valP ← PC + 2 PC ← valP PC ← valP valA ← R [ rA ] valA ← R [ rA ] valB ← R [% rsp ] valB ← R [ rB ] valE ← valB − 8 valE ← valB + valB M [ valE ] ← valA R [ rB ] ← valE
addq pipeline registers write back icode, rA, rB icode, rB, valE icode, rB, valE icode, rB, valA, valB icode, rB icode, rB icode, rB icode, rA, rB icode icode icode icode PC memory icode, dstE, valE execute rB dstE decode PC update fetch addq rA, rB stage addq pipeline registers stage but will make handling data hazards easier redundant with rB + icode icode, dstE, valE icode, dstE, valE icode, dstE, valA, valB icode, dstE, valE icode, rA, rB icode but will make handling data hazards easier redundant with rB + icode icode, dstE, valE icode, dstE, valE icode, dstE, valA, valB icode, rA, rB icode, rB, valE icode, rB, valE icode, rB, valA, valB icode, rB icode, rB icode, rB icode, rA, rB icode redundant with rB + icode icode icode PC write back memory execute decode PC update fetch addq rA, rB stage addq pipeline registers 17 but will make handling data hazards easier icode, dstE, valA, valB 17 icode, rB, valE icode, rB addq pipeline registers 17 but will make handling data hazards easier redundant with rB + icode icode, rB, valE icode, dstE, valE icode, dstE, valA, valB icode, rA, rB icode, rB, valE icode, rB, valE icode, rB, valA, valB icode, rB icode, rB icode, rA, rB addq rA, rB icode icode icode icode PC write back memory execute rB dstE decode PC update fetch addq rA, rB stage icode, dstE, valE fetch memory icode, rB, valA, valB icode, rB icode, rB icode, rB icode, rA, rB icode icode icode icode PC write back 17 dstE decode PC update execute rB icode : ifun ← M 1 [ PC ] icode : ifun ← M 1 [ PC ] valP ← PC + 2 valP ← PC + 2 PC ← valP PC ← valP valA ← R [ rA ] valA ← R [ rA ] valB ← R [ rB ] valB ← R [ rB ] valE ← valB + valB valE ← valB + valB R [ rB ] ← valE R [ rB ] ← valE icode : ifun ← M 1 [ PC ] icode : ifun ← M 1 [ PC ] valP ← PC + 2 valP ← PC + 2 PC ← valP PC ← valP valA ← R [ rA ] valA ← R [ rA ] valB ← R [ rB ] valB ← R [ rB ] dstE ← rB valE ← valB + valB valE ← valB + valB R [ rB ] ← valE R [ dstE ] ← valE
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